{ "Info" "ITDB_TSU_RESULT" "num_ge\[1\]~reg0 numin\[4\] clk 4.044 ns register " "Info: tsu for register \"num_ge\[1\]~reg0\" (data pin = \"numin\[4\]\", clock pin = \"clk\") is 4.044 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.177 ns + Longest pin register " "Info: + Longest pin to register delay is 7.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns numin\[4\] 1 PIN PIN_U3 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_U3; Fanout = 5; PIN Node = 'numin\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { numin[4] } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.095 ns) + CELL(0.607 ns) 7.177 ns num_ge\[1\]~reg0 2 REG LC_X1_Y3_N4 1 " "Info: 2: + IC(5.095 ns) + CELL(0.607 ns) = 7.177 ns; Loc. = LC_X1_Y3_N4; Fanout = 1; REG Node = 'num_ge\[1\]~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.702 ns" { numin[4] num_ge[1]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 29.01 % ) " "Info: Total cell delay = 2.082 ns ( 29.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.095 ns ( 70.99 % ) " "Info: Total interconnect delay = 5.095 ns ( 70.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.177 ns" { numin[4] num_ge[1]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.177 ns" { numin[4] numin[4]~out0 num_ge[1]~reg0 } { 0.000ns 0.000ns 5.095ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns num_ge\[1\]~reg0 2 REG LC_X1_Y3_N4 1 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y3_N4; Fanout = 1; REG Node = 'num_ge\[1\]~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.701 ns" { clk num_ge[1]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clk num_ge[1]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 num_ge[1]~reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.177 ns" { numin[4] num_ge[1]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.177 ns" { numin[4] numin[4]~out0 num_ge[1]~reg0 } { 0.000ns 0.000ns 5.095ns } { 0.000ns 1.475ns 0.607ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clk num_ge[1]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 num_ge[1]~reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk num_shi\[0\] num_shi\[0\]~reg0 9.107 ns register " "Info: tco from clock \"clk\" to destination pin \"num_shi\[0\]\" through register \"num_shi\[0\]~reg0\" is 9.107 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.170 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns num_shi\[0\]~reg0 2 REG LC_X1_Y3_N5 1 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y3_N5; Fanout = 1; REG Node = 'num_shi\[0\]~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.701 ns" { clk num_shi[0]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clk num_shi[0]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 num_shi[0]~reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.713 ns + Longest register pin " "Info: + Longest register to pin delay is 5.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num_shi\[0\]~reg0 1 REG LC_X1_Y3_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y3_N5; Fanout = 1; REG Node = 'num_shi\[0\]~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { num_shi[0]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.605 ns) + CELL(2.108 ns) 5.713 ns num_shi\[0\] 2 PIN PIN_B3 0 " "Info: 2: + IC(3.605 ns) + CELL(2.108 ns) = 5.713 ns; Loc. = PIN_B3; Fanout = 0; PIN Node = 'num_shi\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.713 ns" { num_shi[0]~reg0 num_shi[0] } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 36.90 % ) " "Info: Total cell delay = 2.108 ns ( 36.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.605 ns ( 63.10 % ) " "Info: Total interconnect delay = 3.605 ns ( 63.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.713 ns" { num_shi[0]~reg0 num_shi[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.713 ns" { num_shi[0]~reg0 num_shi[0] } { 0.000ns 3.605ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clk num_shi[0]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 num_shi[0]~reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.713 ns" { num_shi[0]~reg0 num_shi[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.713 ns" { num_shi[0]~reg0 num_shi[0] } { 0.000ns 3.605ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "num_ge\[0\]~reg0 numin\[0\] clk -2.888 ns register " "Info: th for register \"num_ge\[0\]~reg0\" (data pin = \"numin\[0\]\", clock pin = \"clk\") is -2.888 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.246 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns num_ge\[0\]~reg0 2 REG LC_X1_Y18_N2 1 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X1_Y18_N2; Fanout = 1; REG Node = 'num_ge\[0\]~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { clk num_ge[0]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { clk num_ge[0]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { clk clk~out0 num_ge[0]~reg0 } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.149 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.149 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns numin\[0\] 1 PIN PIN_H3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H3; Fanout = 1; PIN Node = 'numin\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { numin[0] } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.565 ns) + CELL(0.115 ns) 6.149 ns num_ge\[0\]~reg0 2 REG LC_X1_Y18_N2 1 " "Info: 2: + IC(4.565 ns) + CELL(0.115 ns) = 6.149 ns; Loc. = LC_X1_Y18_N2; Fanout = 1; REG Node = 'num_ge\[0\]~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.680 ns" { numin[0] num_ge[0]~reg0 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 25.76 % ) " "Info: Total cell delay = 1.584 ns ( 25.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.565 ns ( 74.24 % ) " "Info: Total interconnect delay = 4.565 ns ( 74.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.149 ns" { numin[0] num_ge[0]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.149 ns" { numin[0] numin[0]~out0 num_ge[0]~reg0 } { 0.000ns 0.000ns 4.565ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { clk num_ge[0]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { clk clk~out0 num_ge[0]~reg0 } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.149 ns" { numin[0] num_ge[0]~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.149 ns" { numin[0] numin[0]~out0 num_ge[0]~reg0 } { 0.000ns 0.000ns 4.565ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 14 17:12:39 2008 " "Info: Processing ended: Fri Nov 14 17:12:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}