?? center.tan.rpt
字號:
Classic Timing Analyzer report for center
Fri Nov 14 16:53:58 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+------------+------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+------------+------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.710 ns ; reset ; count[0] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 10.046 ns ; red_b~reg0 ; red_b ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -4.061 ns ; hold ; red_b~reg0 ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 242.01 MHz ( period = 4.132 ns ) ; count[1] ; count[0] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+------------+------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C12F324C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 242.01 MHz ( period = 4.132 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 3.871 ns ;
; N/A ; 242.01 MHz ( period = 4.132 ns ) ; count[1] ; count[3] ; clk ; clk ; None ; None ; 3.871 ns ;
; N/A ; 242.01 MHz ( period = 4.132 ns ) ; count[1] ; count[4] ; clk ; clk ; None ; None ; 3.871 ns ;
; N/A ; 242.01 MHz ( period = 4.132 ns ) ; count[1] ; count[5] ; clk ; clk ; None ; None ; 3.871 ns ;
; N/A ; 242.01 MHz ( period = 4.132 ns ) ; count[1] ; count[2] ; clk ; clk ; None ; None ; 3.871 ns ;
; N/A ; 242.01 MHz ( period = 4.132 ns ) ; count[1] ; count[0] ; clk ; clk ; None ; None ; 3.871 ns ;
; N/A ; 249.81 MHz ( period = 4.003 ns ) ; count[2] ; green_a~reg0 ; clk ; clk ; None ; None ; 3.742 ns ;
; N/A ; 252.78 MHz ( period = 3.956 ns ) ; count[3] ; count[1] ; clk ; clk ; None ; None ; 3.695 ns ;
; N/A ; 252.78 MHz ( period = 3.956 ns ) ; count[3] ; count[3] ; clk ; clk ; None ; None ; 3.695 ns ;
; N/A ; 252.78 MHz ( period = 3.956 ns ) ; count[3] ; count[4] ; clk ; clk ; None ; None ; 3.695 ns ;
; N/A ; 252.78 MHz ( period = 3.956 ns ) ; count[3] ; count[5] ; clk ; clk ; None ; None ; 3.695 ns ;
; N/A ; 252.78 MHz ( period = 3.956 ns ) ; count[3] ; count[2] ; clk ; clk ; None ; None ; 3.695 ns ;
; N/A ; 252.78 MHz ( period = 3.956 ns ) ; count[3] ; count[0] ; clk ; clk ; None ; None ; 3.695 ns ;
; N/A ; 254.26 MHz ( period = 3.933 ns ) ; count[2] ; numb[2]~reg0 ; clk ; clk ; None ; None ; 3.672 ns ;
; N/A ; 254.45 MHz ( period = 3.930 ns ) ; count[3] ; numb[1]~reg0 ; clk ; clk ; None ; None ; 3.669 ns ;
; N/A ; 254.45 MHz ( period = 3.930 ns ) ; count[3] ; numb[2]~reg0 ; clk ; clk ; None ; None ; 3.669 ns ;
; N/A ; 254.45 MHz ( period = 3.930 ns ) ; count[3] ; numb[3]~reg0 ; clk ; clk ; None ; None ; 3.669 ns ;
; N/A ; 254.45 MHz ( period = 3.930 ns ) ; count[3] ; numb[4]~reg0 ; clk ; clk ; None ; None ; 3.669 ns ;
; N/A ; 254.52 MHz ( period = 3.929 ns ) ; count[0] ; numa[4]~reg0 ; clk ; clk ; None ; None ; 3.668 ns ;
; N/A ; 255.23 MHz ( period = 3.918 ns ) ; count[2] ; red_b~reg0 ; clk ; clk ; None ; None ; 3.657 ns ;
; N/A ; 255.43 MHz ( period = 3.915 ns ) ; count[2] ; red_a~reg0 ; clk ; clk ; None ; None ; 3.654 ns ;
; N/A ; 256.08 MHz ( period = 3.905 ns ) ; count[3] ; numa[1]~reg0 ; clk ; clk ; None ; None ; 3.644 ns ;
; N/A ; 256.08 MHz ( period = 3.905 ns ) ; count[3] ; numa[2]~reg0 ; clk ; clk ; None ; None ; 3.644 ns ;
; N/A ; 256.08 MHz ( period = 3.905 ns ) ; count[3] ; numa[3]~reg0 ; clk ; clk ; None ; None ; 3.644 ns ;
; N/A ; 256.08 MHz ( period = 3.905 ns ) ; count[3] ; numa[4]~reg0 ; clk ; clk ; None ; None ; 3.644 ns ;
; N/A ; 259.40 MHz ( period = 3.855 ns ) ; count[1] ; numb[1]~reg0 ; clk ; clk ; None ; None ; 3.594 ns ;
; N/A ; 259.40 MHz ( period = 3.855 ns ) ; count[1] ; numb[2]~reg0 ; clk ; clk ; None ; None ; 3.594 ns ;
; N/A ; 259.40 MHz ( period = 3.855 ns ) ; count[1] ; numb[3]~reg0 ; clk ; clk ; None ; None ; 3.594 ns ;
; N/A ; 259.40 MHz ( period = 3.855 ns ) ; count[1] ; numb[4]~reg0 ; clk ; clk ; None ; None ; 3.594 ns ;
; N/A ; 260.55 MHz ( period = 3.838 ns ) ; count[3] ; green_a~reg0 ; clk ; clk ; None ; None ; 3.577 ns ;
; N/A ; 260.62 MHz ( period = 3.837 ns ) ; count[2] ; numb[0]~reg0 ; clk ; clk ; None ; None ; 3.576 ns ;
; N/A ; 260.76 MHz ( period = 3.835 ns ) ; count[0] ; numa[3]~reg0 ; clk ; clk ; None ; None ; 3.574 ns ;
; N/A ; 261.10 MHz ( period = 3.830 ns ) ; count[1] ; numa[1]~reg0 ; clk ; clk ; None ; None ; 3.569 ns ;
; N/A ; 261.10 MHz ( period = 3.830 ns ) ; count[1] ; numa[2]~reg0 ; clk ; clk ; None ; None ; 3.569 ns ;
; N/A ; 261.10 MHz ( period = 3.830 ns ) ; count[1] ; numa[3]~reg0 ; clk ; clk ; None ; None ; 3.569 ns ;
; N/A ; 261.10 MHz ( period = 3.830 ns ) ; count[1] ; numa[4]~reg0 ; clk ; clk ; None ; None ; 3.569 ns ;
; N/A ; 262.61 MHz ( period = 3.808 ns ) ; count[4] ; count[1] ; clk ; clk ; None ; None ; 3.547 ns ;
; N/A ; 262.61 MHz ( period = 3.808 ns ) ; count[4] ; count[3] ; clk ; clk ; None ; None ; 3.547 ns ;
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