+-------+--------------+------------+---------------+----------+------------+
; N/A   ; None         ; 10.046 ns  ; red_b~reg0    ; red_b    ; clk        ;
; N/A   ; None         ; 9.371 ns   ; flash~reg0    ; flash    ; clk        ;
; N/A   ; None         ; 9.052 ns   ; numa[1]~reg0  ; numa[1]  ; clk        ;
; N/A   ; None         ; 8.022 ns   ; red_a~reg0    ; red_a    ; clk        ;
; N/A   ; None         ; 8.003 ns   ; numa[2]~reg0  ; numa[2]  ; clk        ;
; N/A   ; None         ; 7.832 ns   ; numa[3]~reg0  ; numa[3]  ; clk        ;
; N/A   ; None         ; 7.825 ns   ; yellow_a~reg0 ; yellow_a ; clk        ;
; N/A   ; None         ; 7.572 ns   ; numb[2]~reg0  ; numb[2]  ; clk        ;
; N/A   ; None         ; 7.545 ns   ; numa[0]~reg0  ; numa[0]  ; clk        ;
; N/A   ; None         ; 7.197 ns   ; numb[4]~reg0  ; numb[4]  ; clk        ;
; N/A   ; None         ; 7.173 ns   ; numa[4]~reg0  ; numa[4]  ; clk        ;
; N/A   ; None         ; 7.170 ns   ; numb[0]~reg0  ; numb[0]  ; clk        ;
; N/A   ; None         ; 7.162 ns   ; numb[3]~reg0  ; numb[3]  ; clk        ;
; N/A   ; None         ; 7.156 ns   ; numb[1]~reg0  ; numb[1]  ; clk        ;
; N/A   ; None         ; 6.842 ns   ; green_b~reg0  ; green_b  ; clk        ;
; N/A   ; None         ; 6.788 ns   ; yellow_b~reg0 ; yellow_b ; clk        ;
; N/A   ; None         ; 6.787 ns   ; green_a~reg0  ; green_a  ; clk        ;
+-------+--------------+------------+---------------+----------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+-------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To            ; To Clock ;
+---------------+-------------+-----------+-------+---------------+----------+
; N/A           ; None        ; -4.061 ns ; hold  ; red_b~reg0    ; clk      ;
; N/A           ; None        ; -4.062 ns ; hold  ; red_a~reg0    ; clk      ;
; N/A           ; None        ; -4.073 ns ; hold  ; flash~reg0    ; clk      ;
; N/A           ; None        ; -4.187 ns ; hold  ; green_a~reg0  ; clk      ;
; N/A           ; None        ; -4.252 ns ; hold  ; green_b~reg0  ; clk      ;
; N/A           ; None        ; -4.322 ns ; hold  ; yellow_a~reg0 ; clk      ;
; N/A           ; None        ; -4.367 ns ; hold  ; numa[1]~reg0  ; clk      ;
; N/A           ; None        ; -4.367 ns ; hold  ; numa[2]~reg0  ; clk      ;
; N/A           ; None        ; -4.367 ns ; hold  ; numa[3]~reg0  ; clk      ;
; N/A           ; None        ; -4.367 ns ; hold  ; numa[4]~reg0  ; clk      ;
; N/A           ; None        ; -4.638 ns ; hold  ; yellow_b~reg0 ; clk      ;
; N/A           ; None        ; -4.705 ns ; hold  ; numb[1]~reg0  ; clk      ;
; N/A           ; None        ; -4.705 ns ; hold  ; numb[2]~reg0  ; clk      ;
; N/A           ; None        ; -4.705 ns ; hold  ; numb[3]~reg0  ; clk      ;
; N/A           ; None        ; -4.705 ns ; hold  ; numb[4]~reg0  ; clk      ;
; N/A           ; None        ; -4.705 ns ; hold  ; numb[0]~reg0  ; clk      ;
; N/A           ; None        ; -4.736 ns ; hold  ; numa[0]~reg0  ; clk      ;
; N/A           ; None        ; -5.658 ns ; reset ; count[1]      ; clk      ;
; N/A           ; None        ; -5.658 ns ; reset ; count[3]      ; clk      ;
; N/A           ; None        ; -5.658 ns ; reset ; count[4]      ; clk      ;
; N/A           ; None        ; -5.658 ns ; reset ; count[5]      ; clk      ;
; N/A           ; None        ; -5.658 ns ; reset ; count[2]      ; clk      ;
; N/A           ; None        ; -5.658 ns ; reset ; count[0]      ; clk      ;
+---------------+-------------+-----------+-------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Nov 14 16:53:57 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off center -c center --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 242.01 MHz between source register "count[1]" and destination register "count[1]" (period= 4.132 ns)
    Info: + Longest register to register delay is 3.871 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y3_N2; Fanout = 19; REG Node = 'count[1]'
        Info: 2: + IC(0.826 ns) + CELL(0.442 ns) = 1.268 ns; Loc. = LC_X42_Y3_N2; Fanout = 1; COMB Node = 'Equal0~39'
        Info: 3: + IC(0.436 ns) + CELL(0.292 ns) = 1.996 ns; Loc. = LC_X42_Y3_N0; Fanout = 6; COMB Node = 'process0~0'
        Info: 4: + IC(0.763 ns) + CELL(1.112 ns) = 3.871 ns; Loc. = LC_X41_Y3_N2; Fanout = 19; REG Node = 'count[1]'
        Info: Total cell delay = 1.846 ns ( 47.69 % )
        Info: Total interconnect delay = 2.025 ns ( 52.31 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.111 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 23; CLK Node = 'clk'
            Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X41_Y3_N2; Fanout = 19; REG Node = 'count[1]'
            Info: Total cell delay = 2.180 ns ( 70.07 % )
            Info: Total interconnect delay = 0.931 ns ( 29.93 % )
        Info: - Longest clock path from clock "clk" to source register is 3.111 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 23; CLK Node = 'clk'
            Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X41_Y3_N2; Fanout = 19; REG Node = 'count[1]'
            Info: Total cell delay = 2.180 ns ( 70.07 % )
            Info: Total interconnect delay = 0.931 ns ( 29.93 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "count[1]" (data pin = "reset", clock pin = "clk") is 5.710 ns
    Info: + Longest pin to register delay is 8.784 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_P12; Fanout = 1; PIN Node = 'reset'
        Info: 2: + IC(4.992 ns) + CELL(0.442 ns) = 6.909 ns; Loc. = LC_X42_Y3_N0; Fanout = 6; COMB Node = 'process0~0'
        Info: 3: + IC(0.763 ns) + CELL(1.112 ns) = 8.784 ns; Loc. = LC_X41_Y3_N2; Fanout = 19; REG Node = 'count[1]'
        Info: Total cell delay = 3.029 ns ( 34.48 % )
        Info: Total interconnect delay = 5.755 ns ( 65.52 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 23; CLK Node = 'clk'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X41_Y3_N2; Fanout = 19; REG Node = 'count[1]'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
Info: tco from clock "clk" to destination pin "red_b" through register "red_b~reg0" is 10.046 ns
    Info: + Longest clock path from clock "clk" to source register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 23; CLK Node = 'clk'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X40_Y2_N6; Fanout = 1; REG Node = 'red_b~reg0'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.711 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X40_Y2_N6; Fanout = 1; REG Node = 'red_b~reg0'
        Info: 2: + IC(4.587 ns) + CELL(2.124 ns) = 6.711 ns; Loc. = PIN_P4; Fanout = 0; PIN Node = 'red_b'
        Info: Total cell delay = 2.124 ns ( 31.65 % )
        Info: Total interconnect delay = 4.587 ns ( 68.35 % )
Info: th for register "red_b~reg0" (data pin = "hold", clock pin = "clk") is -4.061 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 23; CLK Node = 'clk'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X40_Y2_N6; Fanout = 1; REG Node = 'red_b~reg0'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.187 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_N10; Fanout = 17; PIN Node = 'hold'
        Info: 2: + IC(5.105 ns) + CELL(0.607 ns) = 7.187 ns; Loc. = LC_X40_Y2_N6; Fanout = 1; REG Node = 'red_b~reg0'
        Info: Total cell delay = 2.082 ns ( 28.97 % )
        Info: Total interconnect delay = 5.105 ns ( 71.03 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Fri Nov 14 16:53:58 2008
    Info: Elapsed time: 00:00:01