{ "Info" "ITDB_TSU_RESULT" "count\[1\] reset clk 5.710 ns register " "Info: tsu for register \"count\[1\]\" (data pin = \"reset\", clock pin = \"clk\") is 5.710 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.784 ns + Longest pin register " "Info: + Longest pin to register delay is 8.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 PIN PIN_P12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_P12; Fanout = 1; PIN Node = 'reset'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.992 ns) + CELL(0.442 ns) 6.909 ns process0~0 2 COMB LC_X42_Y3_N0 6 " "Info: 2: + IC(4.992 ns) + CELL(0.442 ns) = 6.909 ns; Loc. = LC_X42_Y3_N0; Fanout = 6; COMB Node = 'process0~0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.434 ns" { reset process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(1.112 ns) 8.784 ns count\[1\] 3 REG LC_X41_Y3_N2 19 " "Info: 3: + IC(0.763 ns) + CELL(1.112 ns) = 8.784 ns; Loc. = LC_X41_Y3_N2; Fanout = 19; REG Node = 'count\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.875 ns" { process0~0 count[1] } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.029 ns ( 34.48 % ) " "Info: Total cell delay = 3.029 ns ( 34.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.755 ns ( 65.52 % ) " "Info: Total interconnect delay = 5.755 ns ( 65.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.784 ns" { reset process0~0 count[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.784 ns" { reset reset~out0 process0~0 count[1] } { 0.000ns 0.000ns 4.992ns 0.763ns } { 0.000ns 1.475ns 0.442ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.111 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 23; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns count\[1\] 2 REG LC_X41_Y3_N2 19 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X41_Y3_N2; Fanout = 19; REG Node = 'count\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { clk count[1] } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk count[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.784 ns" { reset process0~0 count[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.784 ns" { reset reset~out0 process0~0 count[1] } { 0.000ns 0.000ns 4.992ns 0.763ns } { 0.000ns 1.475ns 0.442ns 1.112ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk count[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk red_b red_b~reg0 10.046 ns register " "Info: tco from clock \"clk\" to destination pin \"red_b\" through register \"red_b~reg0\" is 10.046 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.111 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 23; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns red_b~reg0 2 REG LC_X40_Y2_N6 1 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X40_Y2_N6; Fanout = 1; REG Node = 'red_b~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { clk red_b~reg0 } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 32 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk red_b~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 red_b~reg0 } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 32 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.711 ns + Longest register pin " "Info: + Longest register to pin delay is 6.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns red_b~reg0 1 REG LC_X40_Y2_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X40_Y2_N6; Fanout = 1; REG Node = 'red_b~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { red_b~reg0 } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 32 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.587 ns) + CELL(2.124 ns) 6.711 ns red_b 2 PIN PIN_P4 0 " "Info: 2: + IC(4.587 ns) + CELL(2.124 ns) = 6.711 ns; Loc. = PIN_P4; Fanout = 0; PIN Node = 'red_b'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.711 ns" { red_b~reg0 red_b } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 31.65 % ) " "Info: Total cell delay = 2.124 ns ( 31.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.587 ns ( 68.35 % ) " "Info: Total interconnect delay = 4.587 ns ( 68.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.711 ns" { red_b~reg0 red_b } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.711 ns" { red_b~reg0 red_b } { 0.000ns 4.587ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk red_b~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 red_b~reg0 } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.711 ns" { red_b~reg0 red_b } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.711 ns" { red_b~reg0 red_b } { 0.000ns 4.587ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "red_b~reg0 hold clk -4.061 ns register " "Info: th for register \"red_b~reg0\" (data pin = \"hold\", clock pin = \"clk\") is -4.061 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.111 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 23; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns red_b~reg0 2 REG LC_X40_Y2_N6 1 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X40_Y2_N6; Fanout = 1; REG Node = 'red_b~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { clk red_b~reg0 } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 32 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk red_b~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 red_b~reg0 } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 32 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.187 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns hold 1 PIN PIN_N10 17 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_N10; Fanout = 17; PIN Node = 'hold'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { hold } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.105 ns) + CELL(0.607 ns) 7.187 ns red_b~reg0 2 REG LC_X40_Y2_N6 1 " "Info: 2: + IC(5.105 ns) + CELL(0.607 ns) = 7.187 ns; Loc. = LC_X40_Y2_N6; Fanout = 1; REG Node = 'red_b~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.712 ns" { hold red_b~reg0 } "NODE_NAME" } } { "center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 32 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 28.97 % ) " "Info: Total cell delay = 2.082 ns ( 28.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.105 ns ( 71.03 % ) " "Info: Total interconnect delay = 5.105 ns ( 71.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.187 ns" { hold red_b~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.187 ns" { hold hold~out0 red_b~reg0 } { 0.000ns 0.000ns 5.105ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk red_b~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 red_b~reg0 } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.187 ns" { hold red_b~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.187 ns" { hold hold~out0 red_b~reg0 } { 0.000ns 0.000ns 5.105ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "101 " "Info: Allocated 101 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 14 16:53:58 2008 " "Info: Processing ended: Fri Nov 14 16:53:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}