library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity decoder is
	port(led :in std_logic_vector(3 downto 0);
		 decoder_led : out std_logic_vector(6 downto 0));
end entity;

architecture beha of decoder is
begin
	
	process(led)
	begin
		case led is
				when "0000" => decoder_led<="1111110";
				when "0001" => decoder_led<="0110000";
				when "0010" => decoder_led<="1101101";
				when "0011" => decoder_led<="1111001";
				when "0100" => decoder_led<="0110011";
				when "0101" => decoder_led<="1011011";
				when "0110" => decoder_led<="1011111";
				when "0111" => decoder_led<="1110000";
				when "1000" => decoder_led<="1111111";
				when "1001" => decoder_led<="1111011";
				when "1010" => decoder_led<="1110111";
				when "1011" => decoder_led<="0011111";
				when "1100" => decoder_led<="1001110";
				when "1101" => decoder_led<="0111101";
				when "1110" => decoder_led<="1001111";
				when "1111" => decoder_led<="1000111";
				when others => null;
		end case;
	end process;
end architecture;