C51 COMPILER V7.50   INIT                                                                  10/30/2006 16:14:43 PAGE 1   


C51 COMPILER V7.50, COMPILATION OF MODULE INIT
OBJECT MODULE PLACED IN .\Obj\INIT.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE Source\Comm\INIT.c LARGE OPTIMIZE(6,SPEED) BROWSE INCDIR(.\Include\;.\Sourc
                    -e\;.\Include\Panel\;.\Include\GammaTable\;.\Include\tuner\) DEFINE(T103) DEBUG OBJECTEXTEND PRINT(.\INIT.lst) OBJECT(.\O
                    -bj\INIT.obj)

line level    source

   1          #include "INIT.h"
   2          #include "system.h"
   3          #include "SRC_ctrl.h"
   4          #include "Resolution.h"
   5          #include "TW803Reg.h"
   6          
   7          uCHAR code ucaSignalStdRegP2[6]={
   8          0x0c, 0x18, 0x19, 0x1a, 0x1b, 0x82
   9          };
  10          uCHAR code ucaSignalStdValP2[36]={
  11          //NTSC
  12          0x8a, 0x21, 0xf0, 0x7c, 0x0f, 0x42 ,
  13          //PAL
  14          0x67, 0x2a, 0x09, 0x8a, 0xcb, 0x52 ,
  15          //SECAM
  16          0x80, 0x28, 0xb3, 0x3b, 0xb2, 0x52 ,
  17          //NTSC 4  // Add by Sherman 06'01'26
  18          0x8a, 0x2a, 0x09, 0x8a, 0xcb, 0x42 ,
  19          //PAL_M   // Add by Sherman 06'01'26
  20          0x67, 0x21, 0xe6, 0xef, 0xa3, 0x52 ,
  21          //PAL_CN  // Add by Sherman 06'01'26
  22          0x67, 0x21, 0xf6, 0x94, 0x46, 0x52 ,   
  23          };
  24          
  25          uWORD xdata     uiaSrcMux[15]={
  26          // 0x18,0x19
  27                  0x0000, itypeCVBS,      // Reserved
  28                  0x0100, itypeCVBS,      // CVBS1
  29          //      0x0804, itypeCVBS,      // CVBS1
  30          //      0x2008, itypeCVBS,      // CVBS1
  31                  0x1406, itypeSVIDEO,// Svideo0 
  32          //      0x0006, itypeSVIDEO,// Svideo1 
  33                  0x2A24, itypeRGB,       // VGA
  34          //#ifdef PC_MODE
  35          ////    0x2A24, itypeRGB,       // VGA
  36          //#endif
  37                  0x0600, itypeRGB565,    // RGB565
  38          
  39              0x0100, itypeITU656,        // RGB656
  40          
  41          
  42          #ifdef YPbPr
                      0x2824, itypeYPBPR,// add by Sherman 06'01'11
              #endif
  45          
  46          }; // Input source 5 // set the input mux values here, P0_18, P0_19
  47          
  48          
  49          
  50          /****************************************************************************
  51          *      T10x Register No. and values for System and Tcon initial             *
  52          ****************************************************************************/
  53          //====== InitT10x Register No. and values
C51 COMPILER V7.50   INIT                                                                  10/30/2006 16:14:43 PAGE 2   

  54          REGADRVAL code stInitT10xP0[]={
  55                  //adr           , value
  56          
  57                  0x0A            , 0x60,                                 //ADC_ROFF              // Change by Sherman 06'01'10
  58                  0x0B            , 0x60,                         //ADC_GOFF              // Change by Sherman 06'01'10
  59                  0x0C            , 0x60,                     //ADC_BOFF      // Change by Sherman 06'01'10
  60                  0x1A            , 0x87,                                 //ADC_AGC_SEL_REG
  61                  0xCA            , DODIV,                                //PLLDIV_O
  62                  0xC2            , 0x12,                     //POUT_VSYNC_CTRL_REG       
  63                  //for image quality                                                 
  64                  0x6C            , 0x80,                                 //OP_SAT_REG            
  65                  0x60            , 0x00,                                 //DCTI_BW_REG           
  66                  0x61            , 0x88,//For char clear                 //LUMA_PKCTRL_REG                              
  67                  0x62            , 0x18,//For char clear                 //BP_PKCOEF_REG                       
  68                  0x63            , 0x0F,//For char clear                 //HP_PKCOEF_REG                         
  69                  0x64            , 0x04,//For char clear         //60    //LP_PKCOEF_REG                                
  70                  0x66            , 0x88,//For color clear  enable DCTI   //DCTI_GAINCO_REG                            
  71                  0X1C            , 0xF0,                                 //BLANK_SYNCLV_REG      
  72          
  73                  0x97            , 0x95,                                 //CSC_YCOEF_REG         
  74                  0x98            , 0xCC,                                 //CSC_CrRCOEF_REG               
  75                  0x0D            , 0x28,                         //5     //ADC_GENCTRL_REG               
  76                  0xE0            , 0x92,                                 //PW_MGRCTRL_REG                
  77                  0x11            , 0x05,                                 //YPbPr_CLPCTRL_REG     
  78                  //Source Select--S Video                                        
  79                  0x18            , 0x00,                                 //ASRC_MUX_REG          
  80                  0x19            , 0x07,                                 //YCbCr_SW_REG          
  81                  //Enable CSC                                                            
  82                  0x91            , 0x00,                                 //BTIN_PATTERN_REG      
  83                  //DSP Clock                                                     
  84          #ifdef SEQ_MODE  // For sequential mode, bruce, 2006/01/09
                      0xCB            , (CPH1_PH | PHASE_DIV),
                      0xCC            , (CPH3_PH | CPH2_PH), 
                      0xC8            , DFDIV_S,
                      0xC9            , DIDIV_S,
                      0xCA            , DODIV_S,
              #else
  91                  0xC8            , DFDIV_40,                             //PLLDIV_F   
  92                  0xC9            , DIDIV,                                //PLLDIV_I
  93          #endif
  94                  //DSP Colck Polarity                                            
  95                  0xC1            , 0xc8,                                 //POUT_CTRL3_REG                
  96                  //H&V Main Display Pixel Clock Setted   
  97                  0xDC            ,(H_Size&0xFF),//H Size                 //HMDISP_SIZE_L_REG     
  98                  0xDD            ,(H_Size>>8),                           //HMDISP_SIZE_H_REG     
  99                  0xDE            ,(V_Size&0xFF),//V Size         //20    //VMDISP_SIZE_L_REG     
 100                  0xDF            ,(V_Size>>8),                                   //VMDISP_SIZE_H_REG     
 101                  //H&V Display Pixel Clock Setted 
 102                  
 103          #ifdef _160_234
                      0xcb            , 0x66,
                      0xcc            , 0x42,
                      0x79            , 0x0d,
              #endif  
 108                  0xB0            , DISP_DFLT_HDENS,    //H Start         //DWHS_L_REG            
 109                  0xB1            ,(DISP_DFLT_HDENS>>8),                  //DWHS_H_REG            
 110                  0xB2            , DISP_DFLT_VDENS,    //V Start         //DWVS_L_REG