+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 79      ;
; Total combinational functions     ; 63      ;
;     -- Total 4-input functions    ; 31      ;
;     -- Total 3-input functions    ; 7       ;
;     -- Total 2-input functions    ; 15      ;
;     -- Total 1-input functions    ; 10      ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 35      ;
; Total logic cells in carry chains ; 12      ;
; I/O pins                          ; 13      ;
; Maximum fan-out node              ; rst     ;
; Maximum fan-out                   ; 35      ;
; Total fan-out                     ; 295     ;
; Average fan-out                   ; 3.21    ;
+-----------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------+
; |clock                     ; 79 (0)      ; 35           ; 0           ; 13   ; 0            ; 44 (0)       ; 16 (0)            ; 19 (0)           ; 12 (0)          ; |clock                       ;
;    |chooser:chooser1|      ; 22 (22)     ; 10           ; 0           ; 0    ; 0            ; 12 (12)      ; 3 (3)             ; 7 (7)            ; 0 (0)           ; |clock|chooser:chooser1      ;
;    |counter24:counter24_1| ; 18 (18)     ; 8            ; 0           ; 0    ; 0            ; 10 (10)      ; 4 (4)             ; 4 (4)            ; 4 (4)           ; |clock|counter24:counter24_1 ;
;    |counter60:counter60_1| ; 16 (16)     ; 8            ; 0           ; 0    ; 0            ; 8 (8)        ; 4 (4)             ; 4 (4)            ; 4 (4)           ; |clock|counter60:counter60_1 ;
;    |counter60:counter60_2| ; 17 (17)     ; 9            ; 0           ; 0    ; 0            ; 8 (8)        ; 5 (5)             ; 4 (4)            ; 4 (4)           ; |clock|counter60:counter60_2 ;
;    |decoder:decoder1|      ; 6 (6)       ; 0            ; 0           ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |clock|decoder:decoder1      ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 35    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 28    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 11    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clock|counter24:counter24_1|out[0] ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clock|counter60:counter60_2|out[2] ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clock|counter60:counter60_1|out[2] ;
; 8:1                ; 4 bits    ; 20 LEs        ; 16 LEs               ; 4 LEs                  ; Yes        ; |clock|chooser:chooser1|out[0]      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/clock/clock/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 27 22:16:24 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file chooser.v
    Info: Found entity 1: chooser
Info: Found 1 design units, including 1 entities, in source file clock.v
    Info: Found entity 1: clock
Info: Found 1 design units, including 1 entities, in source file counter24.v
    Info: Found entity 1: counter24
Info: Found 1 design units, including 1 entities, in source file counter60.v
    Info: Found entity 1: counter60
Info: Found 1 design units, including 1 entities, in source file decoder.v
    Info: Found entity 1: decoder
Info: Elaborating entity "clock" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at clock.v(11): object "carry_hour" declared but not used
Info: Elaborating entity "counter60" for hierarchy "counter60:counter60_1"
Warning: Verilog HDL assignment warning at counter60.v(16): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at counter60.v(17): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at counter60.v(21): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at counter60.v(25): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at counter60.v(26): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at counter60.v(28): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "counter24" for hierarchy "counter24:counter24_1"
Warning: Verilog HDL assignment warning at counter24.v(19): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at counter24.v(20): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at counter24.v(22): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "chooser" for hierarchy "chooser:chooser1"
Warning: Verilog HDL assignment warning at chooser.v(14): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at chooser.v(16): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at chooser.v(17): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at chooser.v(25): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "decoder" for hierarchy "decoder:decoder1"
Info: Duplicate registers merged to single register
    Info: Duplicate register "counter60:counter60_1|out[0]" merged to single register "chooser:chooser1|i[0]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "out[0]" stuck at GND
Info: Implemented 92 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 11 output pins
    Info: Implemented 79 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
    Info: Processing ended: Fri Oct 27 22:16:26 2006
    Info: Elapsed time: 00:00:02