{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 27 22:16:24 2006 " "Info: Processing started: Fri Oct 27 22:16:24 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chooser.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file chooser.v" { { "Info" "ISGN_ENTITY_NAME" "1 chooser " "Info: Found entity 1: chooser" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter24.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter24.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter24 " "Info: Found entity 1: counter24" {  } { { "counter24.v" "" { Text "E:/clock/clock/counter24.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter60.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter60.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter60 " "Info: Found entity 1: counter60" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file decoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "decoder.v" "" { Text "E:/clock/clock/decoder.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "carry_hour clock.v(11) " "Info: (10035) Verilog HDL or VHDL information at clock.v(11): object \"carry_hour\" declared but not used" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 11 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter60 counter60:counter60_1 " "Info: Elaborating entity \"counter60\" for hierarchy \"counter60:counter60_1\"" {  } { { "clock.v" "counter60_1" { Text "E:/clock/clock/clock.v" 19 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 counter60.v(16) " "Warning: Verilog HDL assignment warning at counter60.v(16): truncated value with size 32 to match size of target (1)" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 counter60.v(17) " "Warning: Verilog HDL assignment warning at counter60.v(17): truncated value with size 32 to match size of target (8)" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 counter60.v(21) " "Warning: Verilog HDL assignment warning at counter60.v(21): truncated value with size 32 to match size of target (8)" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter60.v(25) " "Warning: Verilog HDL assignment warning at counter60.v(25): truncated value with size 32 to match size of target (4)" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter60.v(26) " "Warning: Verilog HDL assignment warning at counter60.v(26): truncated value with size 32 to match size of target (4)" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter60.v(28) " "Warning: Verilog HDL assignment warning at counter60.v(28): truncated value with size 32 to match size of target (4)" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 28 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter24 counter24:counter24_1 " "Info: Elaborating entity \"counter24\" for hierarchy \"counter24:counter24_1\"" {  } { { "clock.v" "counter24_1" { Text "E:/clock/clock/clock.v" 28 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter24.v(19) " "Warning: Verilog HDL assignment warning at counter24.v(19): truncated value with size 32 to match size of target (4)" {  } { { "counter24.v" "" { Text "E:/clock/clock/counter24.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter24.v(20) " "Warning: Verilog HDL assignment warning at counter24.v(20): truncated value with size 32 to match size of target (4)" {  } { { "counter24.v" "" { Text "E:/clock/clock/counter24.v" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter24.v(22) " "Warning: Verilog HDL assignment warning at counter24.v(22): truncated value with size 32 to match size of target (4)" {  } { { "counter24.v" "" { Text "E:/clock/clock/counter24.v" 22 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "chooser chooser:chooser1 " "Info: Elaborating entity \"chooser\" for hierarchy \"chooser:chooser1\"" {  } { { "clock.v" "chooser1" { Text "E:/clock/clock/clock.v" 36 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 chooser.v(14) " "Warning: Verilog HDL assignment warning at chooser.v(14): truncated value with size 32 to match size of target (3)" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 chooser.v(16) " "Warning: Verilog HDL assignment warning at chooser.v(16): truncated value with size 32 to match size of target (3)" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 chooser.v(17) " "Warning: Verilog HDL assignment warning at chooser.v(17): truncated value with size 32 to match size of target (3)" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 chooser.v(25) " "Warning: Verilog HDL assignment warning at chooser.v(25): truncated value with size 32 to match size of target (4)" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 25 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:decoder1 " "Info: Elaborating entity \"decoder\" for hierarchy \"decoder:decoder1\"" {  } { { "clock.v" "decoder1" { Text "E:/clock/clock/clock.v" 39 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "counter60:counter60_1\|out\[0\] chooser:chooser1\|i\[0\] " "Info: Duplicate register \"counter60:counter60_1\|out\[0\]\" merged to single register \"chooser:chooser1\|i\[0\]\"" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "out\[0\] GND " "Warning: Pin \"out\[0\]\" stuck at GND" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "92 " "Info: Implemented 92 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "79 " "Info: Implemented 79 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 27 22:16:26 2006 " "Info: Processing ended: Fri Oct 27 22:16:26 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}