{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 27 22:10:48 2006 " "Info: Processing started: Fri Oct 27 22:10:48 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "clock EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"clock\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 16 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 16" {  } { { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "counter60:counter60_1\|carry Global clock " "Info: Automatically promoted some destinations of signal \"counter60:counter60_1\|carry\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter60:counter60_1\|carry " "Info: Destination \"counter60:counter60_1\|carry\" may be non-global or may not use global clock" {  } { { "counter60.v" "" { Text "E:/clock/counter60.v" 7 -1 0 } }  } 0}  } { { "counter60.v" "" { Text "E:/clock/counter60.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "counter60:counter60_2\|carry Global clock " "Info: Automatically promoted some destinations of signal \"counter60:counter60_2\|carry\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter60:counter60_2\|carry " "Info: Destination \"counter60:counter60_2\|carry\" may be non-global or may not use global clock" {  } { { "counter60.v" "" { Text "E:/clock/counter60.v" 7 -1 0 } }  } 0}  } { { "counter60.v" "" { Text "E:/clock/counter60.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst Global clock " "Info: Automatically promoted some destinations of signal \"rst\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|sel\[2\] " "Info: Destination \"chooser:chooser1\|sel\[2\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|sel\[1\] " "Info: Destination \"chooser:chooser1\|sel\[1\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|sel\[0\] " "Info: Destination \"chooser:chooser1\|sel\[0\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|out\[3\] " "Info: Destination \"chooser:chooser1\|out\[3\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|out\[2\] " "Info: Destination \"chooser:chooser1\|out\[2\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|out\[1\] " "Info: Destination \"chooser:chooser1\|out\[1\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|out\[0\] " "Info: Destination \"chooser:chooser1\|out\[0\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0}  } { { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst " "Info: Pin \"rst\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { rst } "NODE_NAME" } "" } } { "E:/clock/clock.fld" "" { Floorplan "E:/clock/clock.fld" "" "" { rst } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.244 ns register register " "Info: Estimated most critical path is register to register delay of 3.244 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:counter24_1\|out\[2\] 1 REG LAB_X8_Y8 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y8; Fanout = 5; REG Node = 'counter24:counter24_1\|out\[2\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { counter24:counter24_1|out[2] } "NODE_NAME" } "" } } { "counter24.v" "" { Text "E:/clock/counter24.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(0.442 ns) 1.020 ns chooser:chooser1\|Select~737 2 COMB LAB_X9_Y8 1 " "Info: 2: + IC(0.578 ns) + CELL(0.442 ns) = 1.020 ns; Loc. = LAB_X9_Y8; Fanout = 1; COMB Node = 'chooser:chooser1\|Select~737'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.020 ns" { counter24:counter24_1|out[2] chooser:chooser1|Select~737 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.119 ns) + CELL(0.292 ns) 2.431 ns chooser:chooser1\|Select~738 3 COMB LAB_X9_Y5 1 " "Info: 3: + IC(1.119 ns) + CELL(0.292 ns) = 2.431 ns; Loc. = LAB_X9_Y5; Fanout = 1; COMB Node = 'chooser:chooser1\|Select~738'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.411 ns" { chooser:chooser1|Select~737 chooser:chooser1|Select~738 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.075 ns) + CELL(0.738 ns) 3.244 ns chooser:chooser1\|out\[2\] 4 REG LAB_X9_Y5 6 " "Info: 4: + IC(0.075 ns) + CELL(0.738 ns) = 3.244 ns; Loc. = LAB_X9_Y5; Fanout = 6; REG Node = 'chooser:chooser1\|out\[2\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "0.813 ns" { chooser:chooser1|Select~738 chooser:chooser1|out[2] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns 45.38 % " "Info: Total cell delay = 1.472 ns ( 45.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.772 ns 54.62 % " "Info: Total interconnect delay = 1.772 ns ( 54.62 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "3.244 ns" { counter24:counter24_1|out[2] chooser:chooser1|Select~737 chooser:chooser1|Select~738 chooser:chooser1|out[2] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out\[0\] GND " "Info: Pin out\[0\] has GND driving its datain port" {  } { { "clock.v" "" { Text "E:/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[0\]" } } } } { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { out[0] } "NODE_NAME" } "" } } { "E:/clock/clock.fld" "" { Floorplan "E:/clock/clock.fld" "" "" { out[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 27 22:10:52 2006 " "Info: Processing ended: Fri Oct 27 22:10:52 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}