{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 27 22:10:56 2006 " "Info: Processing started: Fri Oct 27 22:10:56 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter60:counter60_2\|carry " "Info: Detected ripple clock \"counter60:counter60_2\|carry\" as buffer" {  } { { "counter60.v" "" { Text "E:/clock/counter60.v" 7 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "counter60:counter60_2\|carry" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter60:counter60_1\|carry " "Info: Detected ripple clock \"counter60:counter60_1\|carry\" as buffer" {  } { { "counter60.v" "" { Text "E:/clock/counter60.v" 7 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "counter60:counter60_1\|carry" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter24:counter24_1\|out\[1\] register chooser:chooser1\|out\[1\] 74.07 MHz 13.5 ns Internal " "Info: Clock \"clk\" has Internal fmax of 74.07 MHz between source register \"counter24:counter24_1\|out\[1\]\" and destination register \"chooser:chooser1\|out\[1\]\" (period= 13.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.924 ns + Longest register register " "Info: + Longest register to register delay is 3.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:counter24_1\|out\[1\] 1 REG LC_X8_Y8_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y8_N2; Fanout = 6; REG Node = 'counter24:counter24_1\|out\[1\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { counter24:counter24_1|out[1] } "NODE_NAME" } "" } } { "counter24.v" "" { Text "E:/clock/counter24.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.442 ns) 1.700 ns chooser:chooser1\|Select~741 2 COMB LC_X9_Y5_N8 1 " "Info: 2: + IC(1.258 ns) + CELL(0.442 ns) = 1.700 ns; Loc. = LC_X9_Y5_N8; Fanout = 1; COMB Node = 'chooser:chooser1\|Select~741'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.700 ns" { counter24:counter24_1|out[1] chooser:chooser1|Select~741 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.714 ns) + CELL(0.590 ns) 3.004 ns chooser:chooser1\|Select~742 3 COMB LC_X9_Y5_N2 1 " "Info: 3: + IC(0.714 ns) + CELL(0.590 ns) = 3.004 ns; Loc. = LC_X9_Y5_N2; Fanout = 1; COMB Node = 'chooser:chooser1\|Select~742'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.304 ns" { chooser:chooser1|Select~741 chooser:chooser1|Select~742 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.478 ns) 3.924 ns chooser:chooser1\|out\[1\] 4 REG LC_X9_Y5_N4 6 " "Info: 4: + IC(0.442 ns) + CELL(0.478 ns) = 3.924 ns; Loc. = LC_X9_Y5_N4; Fanout = 6; REG Node = 'chooser:chooser1\|out\[1\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "0.920 ns" { chooser:chooser1|Select~742 chooser:chooser1|out[1] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.510 ns 38.48 % " "Info: Total cell delay = 1.510 ns ( 38.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.414 ns 61.52 % " "Info: Total interconnect delay = 2.414 ns ( 61.52 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "3.924 ns" { counter24:counter24_1|out[1] chooser:chooser1|Select~741 chooser:chooser1|Select~742 chooser:chooser1|out[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "3.924 ns" { counter24:counter24_1|out[1] chooser:chooser1|Select~741 chooser:chooser1|Select~742 chooser:chooser1|out[1] } { 0.000ns 1.258ns 0.714ns 0.442ns } { 0.000ns 0.442ns 0.590ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.315 ns - Smallest " "Info: - Smallest clock skew is -9.315 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns chooser:chooser1\|out\[1\] 2 REG LC_X9_Y5_N4 6 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y5_N4; Fanout = 6; REG Node = 'chooser:chooser1\|out\[1\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.261 ns" { clk chooser:chooser1|out[1] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "2.730 ns" { clk chooser:chooser1|out[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 chooser:chooser1|out[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.045 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns counter60:counter60_1\|carry 2 REG LC_X8_Y4_N2 10 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X8_Y4_N2; Fanout = 10; REG Node = 'counter60:counter60_1\|carry'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.485 ns" { clk counter60:counter60_1|carry } "NODE_NAME" } "" } } { "counter60.v" "" { Text "E:/clock/counter60.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.989 ns) + CELL(0.935 ns) 7.878 ns counter60:counter60_2\|carry 3 REG LC_X8_Y6_N2 9 " "Info: 3: + IC(3.989 ns) + CELL(0.935 ns) = 7.878 ns; Loc. = LC_X8_Y6_N2; Fanout = 9; REG Node = 'counter60:counter60_2\|carry'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "4.924 ns" { counter60:counter60_1|carry counter60:counter60_2|carry } "NODE_NAME" } "" } } { "counter60.v" "" { Text "E:/clock/counter60.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.456 ns) + CELL(0.711 ns) 12.045 ns counter24:counter24_1\|out\[1\] 4 REG LC_X8_Y8_N2 6 " "Info: 4: + IC(3.456 ns) + CELL(0.711 ns) = 12.045 ns; Loc. = LC_X8_Y8_N2; Fanout = 6; REG Node = 'counter24:counter24_1\|out\[1\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "4.167 ns" { counter60:counter60_2|carry counter24:counter24_1|out[1] } "NODE_NAME" } "" } } { "counter24.v" "" { Text "E:/clock/counter24.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 33.62 % " "Info: Total cell delay = 4.050 ns ( 33.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.995 ns 66.38 % " "Info: Total interconnect delay = 7.995 ns ( 66.38 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "12.045 ns" { clk counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "12.045 ns" { clk clk~out0 counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[1] } { 0.000ns 0.000ns 0.550ns 3.989ns 3.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "2.730 ns" { clk chooser:chooser1|out[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 chooser:chooser1|out[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "12.045 ns" { clk counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "12.045 ns" { clk clk~out0 counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[1] } { 0.000ns 0.000ns 0.550ns 3.989ns 3.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter24.v" "" { Text "E:/clock/counter24.v" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "3.924 ns" { counter24:counter24_1|out[1] chooser:chooser1|Select~741 chooser:chooser1|Select~742 chooser:chooser1|out[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "3.924 ns" { counter24:counter24_1|out[1] chooser:chooser1|Select~741 chooser:chooser1|Select~742 chooser:chooser1|out[1] } { 0.000ns 1.258ns 0.714ns 0.442ns } { 0.000ns 0.442ns 0.590ns 0.478ns } } } { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "2.730 ns" { clk chooser:chooser1|out[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 chooser:chooser1|out[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "12.045 ns" { clk counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "12.045 ns" { clk clk~out0 counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[1] } { 0.000ns 0.000ns 0.550ns 3.989ns 3.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0}