//dev->devEnabled = 1;    //dev->devNum = cfg->devNum;    DBG_INFO("OK.\n");    return GT_OK;}/******************************************************************************** gvlnSetPortVid** DESCRIPTION:*       This routine Set the port default vlan id.** INPUTS:*       port - logical port number to set.*       vid  - the port vlan id.** OUTPUTS:*       None.** RETURNS:*       GT_OK               - on success*       GT_FAIL             - on error*       GT_BAD_PARAM        - on bad parameters** COMMENTS:** GalTis:********************************************************************************/GT_STATUS gvlnSetPortVid(    IN GT_QD_DEV    *dev,    IN GT_LPORT     port,    IN GT_U16       vid){    GT_STATUS       retVal;         /* Functions return value.      */    GT_U8           phyPort;        /* Physical port.               */    DBG_INFO("gvlnSetPortVid Called.\n");    phyPort = GT_LPORT_2_PORT(port);    retVal = hwSetPortRegField(dev,phyPort,QD_REG_PVID,0,12, vid);    if(retVal != GT_OK)    {        DBG_INFO("Failed.\n");        return retVal;    }    DBG_INFO("OK.\n");    return GT_OK;}/******************************************************************************** gvlnSetPortVlanPorts** DESCRIPTION:*       This routine sets the port VLAN group port membership list.** INPUTS:*       port        - logical port number to set.*       memPorts    - array of logical ports.*       memPortsLen - number of members in memPorts array** OUTPUTS:*       None.** RETURNS:*       GT_OK               - on success*       GT_FAIL             - on error*       GT_BAD_PARAM        - on bad parameters** COMMENTS:** GalTis:********************************************************************************/GT_STATUS gvlnSetPortVlanPorts(    IN GT_QD_DEV *dev,    IN GT_LPORT  port,    IN GT_LPORT  memPorts[],    IN GT_U8     memPortsLen){    GT_STATUS       retVal;         /* Functions return value.      */    GT_U16          data;           /* Data to be set into the      */                                    /* register.                    */    GT_U8           phyPort;        /* Physical port.               */    GT_U8           i;    DBG_INFO("gvlnSetPortVlanPorts Called.\n");    if(memPorts == NULL)    {        DBG_INFO("Failed.\n");        return GT_BAD_PARAM;    }    phyPort = GT_LPORT_2_PORT(port);    data = 0;	if(memPortsLen > dev->numOfPorts)    {        DBG_INFO("Failed (PortsLen Too Big).\n");        return GT_BAD_PARAM;    }    for(i = 0; i < memPortsLen; i++)        data |= (1 << GT_LPORT_2_PORT(memPorts[i]));    /* memPortsLen = 3 for fullsail, =7 for others */    retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_VLAN_MAP,0,dev->numOfPorts,data);    if(retVal != GT_OK)    {        DBG_INFO("Failed.\n");        return retVal;    }    DBG_INFO("OK.\n");    return GT_OK;}/******************************************************************************** hwReadGlobalReg** DESCRIPTION:*       This function reads a switch's global register.** INPUTS:*       regAddr - The register's address.** OUTPUTS:*       data    - The read register's data.** RETURNS:*       GT_OK on success, or*       GT_FAIL otherwise.** COMMENTS:*       None.********************************************************************************/GT_STATUS hwReadGlobalReg(    IN GT_QD_DEV *dev,    IN  GT_U8    regAddr,    OUT GT_U16   *pData){    GT_U8       phyAddr;    GT_STATUS   retVal;    phyAddr = CALC_SMI_DEV_ADDR(dev->baseRegAddr,                                GLOBAL_REGS_START_ADDR);    //retVal = evFFReadMii(dev,phyAddr,regAddr,(GT_U32*)pData);    retVal = evFFReadMii(dev,(unsigned int)(0xF - 0x8),(unsigned int)regAddr,(unsigned int*)pData);	DBG_INFO("read from global register: phyAddr 0x%x, regAddr 0x%x, ",              phyAddr,regAddr);    DBG_INFO("data 0x%x.\n",*pData);    return retVal;}/******************************************************************************** hwGetGlobalRegField** DESCRIPTION:*       This function reads a specified field from a switch's global register.** INPUTS:*       regAddr     - The register's address.*       fieldOffset - The field start bit index. (0 - 15)*       fieldLength - Number of bits to read.** OUTPUTS:*       data        - The read register field.** RETURNS:*       GT_OK on success, or*       GT_FAIL otherwise.** COMMENTS:*       1.  The sum of fieldOffset & fieldLength parameters must be smaller-*           equal to 16.********************************************************************************/GT_STATUS hwGetGlobalRegField(    IN GT_QD_DEV *dev,    IN  GT_U8    regAddr,    IN  GT_U8    fieldOffset,    IN  GT_U8    fieldLength,    OUT GT_U16   *data){    GT_U16 mask;            /* Bits mask to be read */    GT_U16 tmpData;    if(hwReadGlobalReg(dev,regAddr,&tmpData) != GT_OK)        return GT_FAIL;    CALC_MASK(fieldOffset,fieldLength,mask);    tmpData = (tmpData & mask) >> fieldOffset;    *data = tmpData;    DBG_INFO("Read from global register: regAddr 0x%x, ",              regAddr);    DBG_INFO("fOff %d, fLen %d, data 0x%x.\n",fieldOffset,fieldLength,*data);    return GT_OK;}/******************************************************************************** hwWriteGlobalReg** DESCRIPTION:*       This function writes to a switch's global register.** INPUTS:*       regAddr - The register's address.*       data    - The data to be written.** OUTPUTS:*       None.** RETURNS:*       GT_OK on success, or*       GT_FAIL otherwise.** COMMENTS:*       None.********************************************************************************/GT_STATUS hwWriteGlobalReg(    IN GT_QD_DEV *dev,    IN  GT_U8    regAddr,    IN  GT_U16   data){    GT_U8   phyAddr;    phyAddr = CALC_SMI_DEV_ADDR(dev->baseRegAddr,                                GLOBAL_REGS_START_ADDR);    DBG_INFO("Write to global register: phyAddr 0x%x, regAddr 0x%x, ",              phyAddr,regAddr);    DBG_INFO("data 0x%x.\n",data);    return evFFWriteMii(dev,phyAddr,regAddr,data);}/******************************************************************************** hwSetGlobalRegField** DESCRIPTION:*       This function writes to specified field in a switch's global register.** INPUTS:*       regAddr     - The register's address.*       fieldOffset - The field start bit index. (0 - 15)*       fieldLength - Number of bits to write.*       data        - Data to be written.** OUTPUTS:*       None.** RETURNS:*       GT_OK on success, or*       GT_FAIL otherwise.** COMMENTS:*       1.  The sum of fieldOffset & fieldLength parameters must be smaller-*           equal to 16.********************************************************************************/GT_STATUS hwSetGlobalRegField(    IN GT_QD_DEV *dev,    IN  GT_U8    regAddr,    IN  GT_U8    fieldOffset,    IN  GT_U8    fieldLength,    IN  GT_U16   data){    GT_U16 mask;    GT_U16 tmpData;    if(hwReadGlobalReg(dev,regAddr,&tmpData) != GT_OK)        return GT_FAIL;    CALC_MASK(fieldOffset,fieldLength,mask);    /* Set the desired bits to 0.                       */    tmpData &= ~mask;    /* Set the given data into the above reset bits.    */    tmpData |= ((data << fieldOffset) & mask);    DBG_INFO("Write to global register: regAddr 0x%x, ",              regAddr);    DBG_INFO("fieldOff %d, fieldLen %d, data 0x%x.\n",fieldOffset,              fieldLength,data);    return hwWriteGlobalReg(dev,regAddr,tmpData);}/******************************************************************************** gprtClearAllCtr** DESCRIPTION:*       This routine clears all port rx/tx counters.** INPUTS:*       None.** OUTPUTS:*       None.** RETURNS:*       GT_OK   - on success*       GT_FAIL - on error** COMMENTS:*** GalTis:********************************************************************************/GT_STATUS gprtClearAllCtr(    IN GT_QD_DEV    *dev){    IN GT_STATUS     retVal;         /* Functions return value.      */    IN GT_U16        mode;           /* hold counters current mode   */    DBG_INFO("gprtClearAllCtr Called.\n");    /* get counter current mode  */    if(hwGetGlobalRegField(dev,QD_REG_GLOBAL_CONTROL,8,1,&mode) != GT_OK)    {        DBG_INFO("Failed (Get field).\n");        return GT_FAIL;    }    /* write opposite value to reset counter */    if(hwSetGlobalRegField(dev,QD_REG_GLOBAL_CONTROL,8,1,(GT_U16)(1 - mode)) != GT_OK)    {        DBG_INFO("Failed (Get field).\n");        return GT_FAIL;    }    /* restore counters mode */    retVal = hwSetGlobalRegField(dev,QD_REG_GLOBAL_CONTROL,8,1,mode);    DBG_INFO("OK.\n");    return retVal;}/**  Initialize the QuarterDeck. This should be done in BSP driver init routine.*	Since BSP is not combined with QuarterDeck driver, we are doing here.*/GT_STATUS qdStart(void) /* devId is used for simulator only */{	GT_STATUS status;	//int portListIdx = 0;	//GT_LPORT portList[MAX_SWITCH_PORTS] = {0};	//evFFInit(qd_dev);	//cfg.initPorts = GT_FALSE;		//cfg.cpuPortNum = CPU_PORT_NUM;	    qd_dev->cpuPortNum = CPU_PORT_NUM;				if((status = qdLoadDriver(NULL, qd_dev)) != GT_OK)	{				DBG_INFO("qdLoadDriver failed\n");		return status;	}	/*	*  start the QuarterDeck	*/	if (qd_dev->deviceId == GT_88E6063)	{		phyPatch(qd_dev);	}		/* to which VID should we set the CPU_PORT? (1 is temporary)*/	if((status = gvlnSetPortVid(qd_dev, CPU_PORT_NUM, 1)) != GT_OK)	{		DBG_INFO("gprtSetPortVid returned fail.\n");		return status;	}	return GT_OK;    }/* * All ports are connected to all ports!! * port #6 is out of the game  */GT_STATUS starVlan(GT_QD_DEV *dev, unsigned int numOfPorts){	GT_STATUS status = GT_OK;	GT_LPORT port;	GT_LPORT portList[MAX_SWITCH_PORTS];	do {		/* 		*  set Port VLAN Mapping.		*	port 0 <--> 5 VLAN #1.		*	port 1 <--> 5 VLAN #2.		*	port 2 <--> 5 VLAN #3.		*	port 3 <--> 5 VLAN #4.		*	port 4 <--> 5 VLAN #5.		*/		portList[0] = 5;		for (port = 0; port < 5; port++) 		{			/* port #port : set VLAN ID (i+1) */			if((status = gvlnSetPortVid(dev, port, (port+1) )) != GT_OK)				break;			/* port #port : set port 5 */			if((status = gvlnSetPortVlanPorts(dev, port, portList,1)) != GT_OK)				return status;		}	/* assign the VID of the CPU port to 1 ??? */	if((status = gvlnSetPortVid(dev, 5, 1)) != GT_OK)		break;	/* port 5 : set port 0,1,2,3,4 */	portList[0] = 0;	portList[1] = 1;	portList[2] = 2;	portList[3] = 3;	portList[4] = 4;		if((status = gvlnSetPortVlanPorts(dev, 5,portList,5)) != GT_OK)		break;		}while(0);		return GT_OK;}/******************************************************************************** gqosSetPortDefaultTc** DESCRIPTION:*       Sets the default traffic class for a specific port.** INPUTS:*       port      - logical port number*       trafClass - default traffic class of a port.** OUTPUTS:*       None.** RETURNS:*       GT_OK   - on success*       GT_FAIL - on error** COMMENTS:*       None.** GalTis:********************************************************************************/GT_STATUS gcosSetPortDefaultTc(    IN  GT_QD_DEV *dev,    IN GT_LPORT   port,    IN GT_U8      trafClass){    GT_STATUS       retVal;         /* Functions return value.      */    GT_U8           hwPort;         /* the physical port number     */    DBG_INFO("gcosSetPortDefaultTc Called.\n");    /* translate LPORT to hardware port */    hwPort = GT_LPORT_2_PORT(port);    /* check if device supports this feature */    if((retVal = IS_VALID_API_CALL(dev,hwPort, DEV_QoS)) != GT_OK )       return retVal;	    /* Set the default port pri.  */    retVal = hwSetPortRegField(dev,hwPort,QD_REG_PVID,14,2,trafClass);    if(retVal != GT_OK)        DBG_INFO("Failed.\n");    else        DBG_INFO("OK.\n");    return retVal;}GT_STATUS qdInit(void){	GT_STATUS	 status = GT_OK;		unsigned int i;	status = qdStart();	if (GT_OK != status)	{		DBG_INFO("qdStart failed !!!\n");				return status;	}	status = gstpSetPortState(qd_dev, 6, GT_PORT_DISABLE);		if((status = gprtClearAllCtr(qd_dev)) != GT_OK)	{				DBG_INFO("Error in QD init 2\n");		return status;	}  	/*	for (i= 0; i < 5; i++)	{		gprtSetMcRateLimit(qd_dev, i, GT_MC_100_PERCENT_RL);	}	*/		/* Setting port default priority to zero */	/* and disabling IP TOS Priority and and 802.3a TAG */	for (i= 0; i <= 6; i++)	{	  gcosSetPortDefaultTc(qd_dev,i,0);	  //gqosIpPrioMapEn(qd_dev, i, GT_FALSE);	  //gqosUserPrioMapEn(qd_dev, i, GT_FALSE);	  //gprtSetForceFc(qd_dev, i, GT_TRUE);	}	status = starVlan(qd_dev, 6); 	if( status == GT_OK)		DBG_INFO("Successfult QD init!\n");	else		DBG_INFO("Error in QD init!\n");	return status;    }void swdelay(void){	int i;	for (i=0x20000; i; i--);}int setclock(void){unsigned short ControlReg;#define W81_REGS8(x)     (*(volatile unsigned char *)(x))#define W81_REGS16(x)    (*(volatile unsigned short *)(x))#define W81_REGS32(x)    (*(volatile unsigned long *)(x))#define W81_READ_REGS8(reg,val)      ((val) = W81_REGS8(reg))#define W81_WRITE_REGS8(reg,val)     (W81_REGS8(reg) = val)#define W81_WRITE_HWORD(reg,val)     (W81_REGS16(reg) = val)#define W81_READ_HWORD(reg,val)      ((val) = W81_REGS16(reg))#define W81_WRITE_WORD(reg,val)      (W81_REGS32(reg) = val)#define W81_READ_WORD(reg,val)       ((val) = W81_REGS32(reg)) #define CLK_MASK   0x000E#define CLK_132MHZ  0x4#define CLK_88MHZ   0x2#define CLK_44MHZ   0x1#define LBU_CLOCK_SELECT_132MHZ 0x00#define LBU_CLOCK_SELECT_88MHZ  0x01#define LBU_CLOCK_SELECT_44MHZ  0x02#define LBU_CLOCK_SELECT_22MHZ  0x03		/* Set the CPU clock speed and corresponding LBU clock select. */	W81_READ_HWORD(0x80002002,ControlReg);#ifdef ENABLE_88MHZ_CLK	W81_WRITE_HWORD(0x80002002,((ControlReg & ~CLK_MASK) | CLK_88MHZ << 1));	W81_WRITE_REGS8(0x8000c008, LBU_CLOCK_SELECT_88MHZ); #elif ENABLE_132MHZ_CLK	W81_WRITE_HWORD(0x80002002,((ControlReg &  ~CLK_MASK) | CLK_132MHZ << 1));	W81_WRITE_REGS8(0x8000c008, LBU_CLOCK_SELECT_132MHZ);#endif	/* Set PLL or low speed peripheral clock will not be 8MHz. */    W81_WRITE_WORD(0x8000a444, 0x1);	return 1;}