<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_ReceiveFrame">AT91F_PDC_ReceiveFrame</a></b></font></td><td><font size="-1">Close PDC: disable TX and RX reset transfer descriptors</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_SetTx">AT91F_PDC_SetTx</a></b></font></td><td><font size="-1">Set the transmit transfer descriptor</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_DisableRx">AT91F_PDC_DisableRx</a></b></font></td><td><font size="-1">Disable receive</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_EnableTx">AT91F_PDC_EnableTx</a></b></font></td><td><font size="-1">Enable transmit</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_IsNextRxEmpty">AT91F_PDC_IsNextRxEmpty</a></b></font></td><td><font size="-1">Test if the next transfer descriptor has been moved to the current td</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_DisableTx">AT91F_PDC_DisableTx</a></b></font></td><td><font size="-1">Disable transmit</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_Close">AT91F_PDC_Close</a></b></font></td><td><font size="-1">Close PDC: disable TX and RX reset transfer descriptors</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_IsTxEmpty">AT91F_PDC_IsTxEmpty</a></b></font></td><td><font size="-1">Test if the current transfer descriptor has been sent</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_SetNextRx">AT91F_PDC_SetNextRx</a></b></font></td><td><font size="-1">Set the next receive transfer descriptor</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_SetNextTx">AT91F_PDC_SetNextTx</a></b></font></td><td><font size="-1">Set the next transmit transfer descriptor</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_IsNextTxEmpty">AT91F_PDC_IsNextTxEmpty</a></b></font></td><td><font size="-1">Test if the next transfer descriptor has been moved to the current td</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_Open">AT91F_PDC_Open</a></b></font></td><td><font size="-1">Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_SendFrame">AT91F_PDC_SendFrame</a></b></font></td><td><font size="-1">Close PDC: disable TX and RX reset transfer descriptors</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_PDC_IsRxEmpty">AT91F_PDC_IsRxEmpty</a></b></font></td><td><font size="-1">Test if the current transfer descriptor has been filled</font></td></tr>
</null></table></null><h2>PDC Register Description</h2>
<null><a name="PDC_RPR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_RPR  <i>Receive Pointer Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_RPR">AT91C_DBGU_RPR</a></i> 0xFFFFF300</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_RPR">AT91C_SPI_RPR</a></i> 0xFFFE0100</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_RPR">AT91C_ADC_RPR</a></i> 0xFFFD8100</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_RPR">AT91C_SSC_RPR</a></i> 0xFFFD4100</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_RPR">AT91C_US1_RPR</a></i> 0xFFFC4100</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_RPR">AT91C_US0_RPR</a></i> 0xFFFC0100</font></null></ul><br>This register must be loaded with the address of the receive buffer<a name="PDC_RCR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_RCR  <i>Receive Counter Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_RCR">AT91C_DBGU_RCR</a></i> 0xFFFFF304</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_RCR">AT91C_SPI_RCR</a></i> 0xFFFE0104</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_RCR">AT91C_ADC_RCR</a></i> 0xFFFD8104</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_RCR">AT91C_SSC_RCR</a></i> 0xFFFD4104</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_RCR">AT91C_US1_RCR</a></i> 0xFFFC4104</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_RCR">AT91C_US0_RCR</a></i> 0xFFFC0104</font></null></ul><br>This register must be loaded with the size of the receive buffer.<br>0 = Stop peripheral data transfer to the receiver<br>1 - 65535 = Start peripheral data transfer if corresponding periph_px_rdy is active<a name="PDC_TPR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_TPR  <i>Transmit Pointer Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_TPR">AT91C_DBGU_TPR</a></i> 0xFFFFF308</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_TPR">AT91C_SPI_TPR</a></i> 0xFFFE0108</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_TPR">AT91C_ADC_TPR</a></i> 0xFFFD8108</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_TPR">AT91C_SSC_TPR</a></i> 0xFFFD4108</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_TPR">AT91C_US1_TPR</a></i> 0xFFFC4108</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_TPR">AT91C_US0_TPR</a></i> 0xFFFC0108</font></null></ul><br>This register must be loaded with the address of the transmit buffer<a name="PDC_TCR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_TCR  <i>Transmit Counter Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_TCR">AT91C_DBGU_TCR</a></i> 0xFFFFF30C</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_TCR">AT91C_SPI_TCR</a></i> 0xFFFE010C</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_TCR">AT91C_ADC_TCR</a></i> 0xFFFD810C</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_TCR">AT91C_SSC_TCR</a></i> 0xFFFD410C</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_TCR">AT91C_US1_TCR</a></i> 0xFFFC410C</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_TCR">AT91C_US0_TCR</a></i> 0xFFFC010C</font></null></ul><br>TXCTR must be loaded with the size of the transmit buffer.<br>0 = Stop peripheral data transfer to the transmitter<br>1- 65535 = Start peripheral data transfer if corresponding periph_tx_rdy is active<a name="PDC_RNPR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_RNPR  <i>Receive Next Pointer Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_RNPR">AT91C_DBGU_RNPR</a></i> 0xFFFFF310</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_RNPR">AT91C_SPI_RNPR</a></i> 0xFFFE0110</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_RNPR">AT91C_ADC_RNPR</a></i> 0xFFFD8110</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_RNPR">AT91C_SSC_RNPR</a></i> 0xFFFD4110</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_RNPR">AT91C_US1_RNPR</a></i> 0xFFFC4110</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_RNPR">AT91C_US0_RNPR</a></i> 0xFFFC0110</font></null></ul><br>contains the address of the next buffer to fill with received data when the current one is completed.<a name="PDC_RNCR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_RNCR  <i>Receive Next Counter Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_RNCR">AT91C_DBGU_RNCR</a></i> 0xFFFFF314</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_RNCR">AT91C_SPI_RNCR</a></i> 0xFFFE0114</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_RNCR">AT91C_ADC_RNCR</a></i> 0xFFFD8114</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_RNCR">AT91C_SSC_RNCR</a></i> 0xFFFD4114</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_RNCR">AT91C_US1_RNCR</a></i> 0xFFFC4114</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_RNCR">AT91C_US0_RNCR</a></i> 0xFFFC0114</font></null></ul><br>This register contains the next buffer maximum size.<a name="PDC_TNPR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_TNPR  <i>Transmit Next Pointer Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_TNPR">AT91C_DBGU_TNPR</a></i> 0xFFFFF318</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_TNPR">AT91C_SPI_TNPR</a></i> 0xFFFE0118</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_TNPR">AT91C_ADC_TNPR</a></i> 0xFFFD8118</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_TNPR">AT91C_SSC_TNPR</a></i> 0xFFFD4118</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_TNPR">AT91C_US1_TNPR</a></i> 0xFFFC4118</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_TNPR">AT91C_US0_TNPR</a></i> 0xFFFC0118</font></null></ul><br>This register contains the address of the next buffer from where to read data when the current one is complete.<a name="PDC_TNCR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_TNCR  <i>Transmit Next Counter Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_TNCR">AT91C_DBGU_TNCR</a></i> 0xFFFFF31C</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_TNCR">AT91C_SPI_TNCR</a></i> 0xFFFE011C</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_TNCR">AT91C_ADC_TNCR</a></i> 0xFFFD811C</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_TNCR">AT91C_SSC_TNCR</a></i> 0xFFFD411C</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_TNCR">AT91C_US1_TNCR</a></i> 0xFFFC411C</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_TNCR">AT91C_US0_TNCR</a></i> 0xFFFC011C</font></null></ul><br>This register contains the next transmit buffer size.<a name="PDC_PTCR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_PTCR  <i>PDC Transfer Control Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_PTCR">AT91C_DBGU_PTCR</a></i> 0xFFFFF320</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_PTCR">AT91C_SPI_PTCR</a></i> 0xFFFE0120</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_PTCR">AT91C_ADC_PTCR</a></i> 0xFFFD8120</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_PTCR">AT91C_SSC_PTCR</a></i> 0xFFFD4120</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_PTCR">AT91C_US1_PTCR</a></i> 0xFFFC4120</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_PTCR">AT91C_US0_PTCR</a></i> 0xFFFC0120</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="PDC_RXTEN"></a><b>PDC_RXTEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_PDC_RXTEN">AT91C_PDC_RXTEN</a></font></td><td><b>Receiver Transfer Enable</b><br>PDC_PTCR<br>0 = No effect.<br>1 = Enables the receiver PDC2 transfer requests if RXTDIS is not set.<br>PDC_PTSR<br>0 = Receiver PDC2 transfer requests are disabled.<br>1 = Receiver PDC2 transfer requests are enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="PDC_RXTDIS"></a><b>PDC_RXTDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_PDC_RXTDIS">AT91C_PDC_RXTDIS</a></font></td><td><b>Receiver Transfer Disable</b><br>0 = No effect.<br>1 = Disables the receiver PDC2 transfer requests.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="PDC_TXTEN"></a><b>PDC_TXTEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_PDC_TXTEN">AT91C_PDC_TXTEN</a></font></td><td><b>Transmitter Transfer Enable</b><br>PDC_PTCR<br>0 = No effect.<br>1 = Enables the transmitter PDC2 transfer requests.<br>PDC_PTSR<br>0 = Transmitter PDC2 transfer requests are disabled.<br>1 = Transmitter PDC2 transfer requests are enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="PDC_TXTDIS"></a><b>PDC_TXTDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_PDC_TXTDIS">AT91C_PDC_TXTDIS</a></font></td><td><b>Transmitter Transfer Disable</b><br>0 = No effect.<br>1 = Disables the transmitter PDC2 transfer requests.</td></tr>
</null></table>
<a name="PDC_PTSR"></a><h4><a href="#PDC">PDC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> PDC_PTSR  <i>PDC Transfer Status Register</i></h4><ul><null><font size="-2"><li><b>PDC_DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_PTSR">AT91C_DBGU_PTSR</a></i> 0xFFFFF324</font><font size="-2"><li><b>PDC_SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_PTSR">AT91C_SPI_PTSR</a></i> 0xFFFE0124</font><font size="-2"><li><b>PDC_ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_PTSR">AT91C_ADC_PTSR</a></i> 0xFFFD8124</font><font size="-2"><li><b>PDC_SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_PTSR">AT91C_SSC_PTSR</a></i> 0xFFFD4124</font><font size="-2"><li><b>PDC_US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_PTSR">AT91C_US1_PTSR</a></i> 0xFFFC4124</font><font size="-2"><li><b>PDC_US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_PTSR">AT91C_US0_PTSR</a></i> 0xFFFC0124</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="PDC_RXTEN"></a><b>PDC_RXTEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_PDC_RXTEN">AT91C_PDC_RXTEN</a></font></td><td><b>Receiver Transfer Enable</b><br>PDC_PTCR<br>0 = No effect.<br>1 = Enables the receiver PDC2 transfer requests if RXTDIS is not set.<br>PDC_PTSR<br>0 = Receiver PDC2 transfer requests are disabled.<br>1 = Receiver PDC2 transfer requests are enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="PDC_TXTEN"></a><b>PDC_TXTEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_PDC_TXTEN">AT91C_PDC_TXTEN</a></font></td><td><b>Transmitter Transfer Enable</b><br>PDC_PTCR<br>0 = No effect.<br>1 = Enables the transmitter PDC2 transfer requests.<br>PDC_PTSR<br>0 = Transmitter PDC2 transfer requests are disabled.<br>1 = Transmitter PDC2 transfer requests are enabled.</td></tr>
</null></table>
</null><hr></html>