<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_UDP_EpStatus">AT91F_UDP_EpStatus</a></b></font></td><td><font size="-1">Return the endpoint CSR register</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_UDP_IsInterruptMasked">AT91F_UDP_IsInterruptMasked</a></b></font></td><td><font size="-1">Test if UDP Interrupt is Masked </font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_UDP_GetInterruptMaskStatus">AT91F_UDP_GetInterruptMaskStatus</a></b></font></td><td><font size="-1">Return UDP Interrupt Mask Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_UDP_GetState">AT91F_UDP_GetState</a></b></font></td><td><font size="-1">return UDP Device state</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_UDP_SetState">AT91F_UDP_SetState</a></b></font></td><td><font size="-1">Set UDP Device state</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_UDP_EnableEp">AT91F_UDP_EnableEp</a></b></font></td><td><font size="-1">Enable Endpoint</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_UDP_EpEndOfWr">AT91F_UDP_EpEndOfWr</a></b></font></td><td><font size="-1">Notify the UDP that values in DPR are ready to be sent</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_UDP_DisableIt">AT91F_UDP_DisableIt</a></b></font></td><td><font size="-1">Disable UDP IT</font></td></tr>
</null></table></null><h2>UDP Register Description</h2>
<null><a name="UDP_FRM_NUM"></a><h4><a href="#UDP">UDP</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> UDP_FRM_NUM  <i>Frame Number Register</i></h4><ul><null><font size="-2"><li><b>UDP</b> <i><a href="AT91SAM7S256_h.html#AT91C_UDP_NUM">AT91C_UDP_NUM</a></i> 0xFFFB0000</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">10..0</td><td align="CENTER"><a name="UDP_FRM_NUM"></a><b>UDP_FRM_NUM</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_FRM_NUM">AT91C_UDP_FRM_NUM</a></font></td><td><b>Frame Number as Defined in the Packet Field Formats</b><br>This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP(Start of Frame End of Packet).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="UDP_FRM_ERR"></a><b>UDP_FRM_ERR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_FRM_ERR">AT91C_UDP_FRM_ERR</a></font></td><td><b>Frame Error</b><br>This bit is set at SOF_EOP when the SOF packet is received containing an error.<br>This bit is reset upon receipt of SOF_PID.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="UDP_FRM_OK"></a><b>UDP_FRM_OK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_FRM_OK">AT91C_UDP_FRM_OK</a></font></td><td><b>Frame OK</b><br>This bit is set at SOF_EOP when the SOF packet is received without any error.<br>This bit is reset upon receipt of SOF_PID (Packet Identification).<br>In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP.<br>Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L.</td></tr>
</null></table>
<a name="UDP_GLBSTATE"></a><h4><a href="#UDP">UDP</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> UDP_GLBSTATE  <i>Global State Register</i></h4><ul><null><font size="-2"><li><b>UDP</b> <i><a href="AT91SAM7S256_h.html#AT91C_UDP_GLBSTATE">AT91C_UDP_GLBSTATE</a></i> 0xFFFB0004</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="UDP_FADDEN"></a><b>UDP_FADDEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_FADDEN">AT91C_UDP_FADDEN</a></font></td><td><b>Function Address Enable</b><br>Read:<br>0 = Device is not in address state.<br>1 = Device is in address state.<br>Write:<br>0 = No effect, only a reset can bring back a device to the default state.<br>1 = Set device in address state. This occurs after a successful Set Address request. Beforehand, the USB_FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FAD-DEN. Please refer to chapter 9 of the Universal Serial Bus Specification, Rev. 1.1 to get more details.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="UDP_CONFG"></a><b>UDP_CONFG</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_CONFG">AT91C_UDP_CONFG</a></font></td><td><b>Configured</b><br>Read:<br>0 = Device is not in configured state.<br>1 = Device is in configured state.<br>Write:<br>0 = Set device in a nonconfigured state<br>1 = Set device in configured state.<br>The device is set in configured state when it is in address state and receives a successful Set Configuration request. Please refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 1.1 to get more details.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="UDP_ESR"></a><b>UDP_ESR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_ESR">AT91C_UDP_ESR</a></font></td><td><b>Enable Send Resume</b><br>0 = Disable the remote wake up.<br>1 = Enable function's remote wake up.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="UDP_RSMINPR"></a><b>UDP_RSMINPR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_RSMINPR">AT91C_UDP_RSMINPR</a></font></td><td><b>A Resume Has Been Sent to the Host</b><br>Read:<br>0 = No effect.<br>1 = A Resume has been received from the host during Remote Wake Up feature.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="UDP_RMWUPE"></a><b>UDP_RMWUPE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_RMWUPE">AT91C_UDP_RMWUPE</a></font></td><td><b>Remote Wake Up Enable</b><br>0 = Must be clmeared after any HOST packet or SOF interrupt.<br> 1 = Enable the K-state if the function's remote wake up feature is enabled.</td></tr>
</null></table>
<a name="UDP_FADDR"></a><h4><a href="#UDP">UDP</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> UDP_FADDR  <i>Function Address Register</i></h4><ul><null><font size="-2"><li><b>UDP</b> <i><a href="AT91SAM7S256_h.html#AT91C_UDP_FADDR">AT91C_UDP_FADDR</a></i> 0xFFFB0008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="UDP_FADD"></a><b>UDP_FADD</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_FADD">AT91C_UDP_FADD</a></font></td><td><b>Function Address Value</b><br>The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Please refer to the Universal Serial Bus Specifica-tion, Rev. 1.1 to get more information. After power up, or reset, the function address value is set to 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="UDP_FEN"></a><b>UDP_FEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_FEN">AT91C_UDP_FEN</a></font></td><td><b>Function Enable</b><br>Read:<br>0 = Function endpoint disabled.<br>1 = Function endpoint enabled.<br>Write:<br>0 = Disable function endpoint.<br>1 = Default value.<br>The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller will set this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host.</td></tr>
</null></table>
<a name="UDP_IER"></a><h4><a href="#UDP">UDP</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> UDP_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>UDP</b> <i><a href="AT91SAM7S256_h.html#AT91C_UDP_IER">AT91C_UDP_IER</a></i> 0xFFFB0010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="UDP_EPINT0"></a><b>UDP_EPINT0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_EPINT0">AT91C_UDP_EPINT0</a></font></td><td><b>Endpoint 0 Interrupt</b><br>0 = No Endpoint0 Interrupt pending.<br>1 = Endpoint0 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR0:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding USB_CSR0 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="UDP_EPINT1"></a><b>UDP_EPINT1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_EPINT1">AT91C_UDP_EPINT1</a></font></td><td><b>Endpoint 0 Interrupt</b><br>0 = No Endpoint1 Interrupt pending.<br>1 = Endpoint1 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR1:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding USB_CSR1 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="UDP_EPINT2"></a><b>UDP_EPINT2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_EPINT2">AT91C_UDP_EPINT2</a></font></td><td><b>Endpoint 2 Interrupt</b><br>0 = No Endpoint2 Interrupt pending.<br>1 = Endpoint2 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR2:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding USB_CSR2 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="UDP_EPINT3"></a><b>UDP_EPINT3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_EPINT3">AT91C_UDP_EPINT3</a></font></td><td><b>Endpoint 3 Interrupt</b><br>0 = No Endpoint3 Interrupt pending.<br>1 = Endpoint3 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR3:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding USB_CSR3 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="UDP_RXSUSP"></a><b>UDP_RXSUSP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_RXSUSP">AT91C_UDP_RXSUSP</a></font></td><td><b>USB Suspend Interrupt</b><br>0 = No USB Suspend Interrupt pending.<br>1 = USB Suspend Interrupt has been raised.<br>The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="UDP_RXRSM"></a><b>UDP_RXRSM</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_RXRSM">AT91C_UDP_RXRSM</a></font></td><td><b>USB Resume Interrupt</b><br>0 = No USB Resume Interrupt pending.<br>1 =USB Resume Interrupt has been raised.<br>The USB device sets this bit when a USB resume signal is detected at its port.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="UDP_EXTRSM"></a><b>UDP_EXTRSM</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_EXTRSM">AT91C_UDP_EXTRSM</a></font></td><td><b>USB External Resume Interrupt</b><br>0 = No External Resume Interrupt pending.<br>1 = External Resume Interrupt has been raised.<br>This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="UDP_SOFINT"></a><b>UDP_SOFINT</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_SOFINT">AT91C_UDP_SOFINT</a></font></td><td><b>USB Start Of frame Interrupt</b><br>0 = No Start of Frame Interrupt pending.<br>1 = Start of Frame Interrupt has been raised.<br>This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="UDP_WAKEUP"></a><b>UDP_WAKEUP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_WAKEUP">AT91C_UDP_WAKEUP</a></font></td><td><b>USB Resume Interrupt</b><br>0 = No Wakeup Interrupt pending.<br>1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.</td></tr>
</null></table>
<a name="UDP_IDR"></a><h4><a href="#UDP">UDP</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> UDP_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>UDP</b> <i><a href="AT91SAM7S256_h.html#AT91C_UDP_IDR">AT91C_UDP_IDR</a></i> 0xFFFB0014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="UDP_EPINT0"></a><b>UDP_EPINT0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_EPINT0">AT91C_UDP_EPINT0</a></font></td><td><b>Endpoint 0 Interrupt</b><br>0 = No Endpoint0 Interrupt pending.<br>1 = Endpoint0 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR0:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding USB_CSR0 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="UDP_EPINT1"></a><b>UDP_EPINT1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_EPINT1">AT91C_UDP_EPINT1</a></font></td><td><b>Endpoint 0 Interrupt</b><br>0 = No Endpoint1 Interrupt pending.<br>1 = Endpoint1 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR1:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding USB_CSR1 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="UDP_EPINT2"></a><b>UDP_EPINT2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_UDP_EPINT2">AT91C_UDP_EPINT2</a></font></td><td><b>Endpoint 2 Interrupt</b><br>0 = No Endpoint2 Interrupt pending.<br>1 = Endpoint2 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR2:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding USB_CSR2 bit.</td></tr>