?? pic16f873.h
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//// Register Declarations for Microchip 16F873 Processor////// This header file was automatically generated by://// inc2h.pl V1.6//// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved//// SDCC is licensed under the GNU Public license (GPL) v2. Note that// this license covers the code to the compiler and other executables,// but explicitly does not cover any code or objects generated by sdcc.// We have not yet decided on a license for the run time libraries, but// it will not put any requirements on code linked against it. See:// // http://www.gnu.org/copyleft/gpl/html//// See http://sdcc.sourceforge.net/ for the latest information on sdcc.//// #ifndef P16F873_H#define P16F873_H//// Register addresses.//#define INDF_ADDR 0x0000#define TMR0_ADDR 0x0001#define PCL_ADDR 0x0002#define STATUS_ADDR 0x0003#define FSR_ADDR 0x0004#define PORTA_ADDR 0x0005#define PORTB_ADDR 0x0006#define PORTC_ADDR 0x0007#define PCLATH_ADDR 0x000A#define INTCON_ADDR 0x000B#define PIR1_ADDR 0x000C#define PIR2_ADDR 0x000D#define TMR1L_ADDR 0x000E#define TMR1H_ADDR 0x000F#define T1CON_ADDR 0x0010#define TMR2_ADDR 0x0011#define T2CON_ADDR 0x0012#define SSPBUF_ADDR 0x0013#define SSPCON_ADDR 0x0014#define CCPR1L_ADDR 0x0015#define CCPR1H_ADDR 0x0016#define CCP1CON_ADDR 0x0017#define RCSTA_ADDR 0x0018#define TXREG_ADDR 0x0019#define RCREG_ADDR 0x001A#define CCPR2L_ADDR 0x001B#define CCPR2H_ADDR 0x001C#define CCP2CON_ADDR 0x001D#define ADRESH_ADDR 0x001E#define ADCON0_ADDR 0x001F#define OPTION_REG_ADDR 0x0081#define TRISA_ADDR 0x0085#define TRISB_ADDR 0x0086#define TRISC_ADDR 0x0087#define PIE1_ADDR 0x008C#define PIE2_ADDR 0x008D#define PCON_ADDR 0x008E#define SSPCON2_ADDR 0x0091#define PR2_ADDR 0x0092#define SSPADD_ADDR 0x0093#define SSPSTAT_ADDR 0x0094#define TXSTA_ADDR 0x0098#define SPBRG_ADDR 0x0099#define ADRESL_ADDR 0x009E#define ADCON1_ADDR 0x009F#define EEDATA_ADDR 0x010C#define EEADR_ADDR 0x010D#define EEDATH_ADDR 0x010E#define EEADRH_ADDR 0x010F#define EECON1_ADDR 0x018C#define EECON2_ADDR 0x018D//// Memory organization.//#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2// LIST// P16F873.INC Standard Header File, Version 1.00 Microchip Technology, Inc.// NOLIST// This header file defines configurations, registers, and other useful bits of// information for the PIC16F873 microcontroller. These names are taken to match // the data sheets as closely as possible. // Note that the processor must be selected before this file is // included. The processor may be selected the following ways:// 1. Command line switch:// C:\ MPASM MYFILE.ASM /PIC16F873// 2. LIST directive in the source file// LIST P=PIC16F873// 3. Processor Type entry in the MPASM full-screen interface//==========================================================================//// Revision History////==========================================================================//Rev: Date: Reason://1.12 01/12/00 Changed some bit names, a register name, configuration bits// to match datasheet (DS30292B)//1.11 10/18/98 Changes to file registers to match updated DOS//1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1 //1.00 08/07/98 Initial Release//==========================================================================//// Verify Processor////==========================================================================// IFNDEF __16F873// MESSG "Processor-header file mismatch. Verify selected processor."// ENDIF//==========================================================================//// Register Definitions////==========================================================================#define W 0x0000#define F 0x0001//----- Register Files------------------------------------------------------extern __data __at (INDF_ADDR) volatile char INDF;extern __sfr __at (TMR0_ADDR) TMR0;extern __data __at (PCL_ADDR) volatile char PCL;extern __sfr __at (STATUS_ADDR) STATUS;extern __sfr __at (FSR_ADDR) FSR;extern __sfr __at (PORTA_ADDR) PORTA;extern __sfr __at (PORTB_ADDR) PORTB;extern __sfr __at (PORTC_ADDR) PORTC;extern __sfr __at (PCLATH_ADDR) PCLATH;extern __sfr __at (INTCON_ADDR) INTCON;extern __sfr __at (PIR1_ADDR) PIR1;extern __sfr __at (PIR2_ADDR) PIR2;extern __sfr __at (TMR1L_ADDR) TMR1L;extern __sfr __at (TMR1H_ADDR) TMR1H;extern __sfr __at (T1CON_ADDR) T1CON;extern __sfr __at (TMR2_ADDR) TMR2;extern __sfr __at (T2CON_ADDR) T2CON;extern __sfr __at (SSPBUF_ADDR) SSPBUF;extern __sfr __at (SSPCON_ADDR) SSPCON;extern __sfr __at (CCPR1L_ADDR) CCPR1L;extern __sfr __at (CCPR1H_ADDR) CCPR1H;extern __sfr __at (CCP1CON_ADDR) CCP1CON;extern __sfr __at (RCSTA_ADDR) RCSTA;extern __sfr __at (TXREG_ADDR) TXREG;extern __sfr __at (RCREG_ADDR) RCREG;extern __sfr __at (CCPR2L_ADDR) CCPR2L;extern __sfr __at (CCPR2H_ADDR) CCPR2H;extern __sfr __at (CCP2CON_ADDR) CCP2CON;extern __sfr __at (ADRESH_ADDR) ADRESH;extern __sfr __at (ADCON0_ADDR) ADCON0;extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;extern __sfr __at (TRISA_ADDR) TRISA;extern __sfr __at (TRISB_ADDR) TRISB;extern __sfr __at (TRISC_ADDR) TRISC;extern __sfr __at (PIE1_ADDR) PIE1;extern __sfr __at (PIE2_ADDR) PIE2;extern __sfr __at (PCON_ADDR) PCON;extern __sfr __at (SSPCON2_ADDR) SSPCON2;extern __sfr __at (PR2_ADDR) PR2;extern __sfr __at (SSPADD_ADDR) SSPADD;extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;extern __sfr __at (TXSTA_ADDR) TXSTA;extern __sfr __at (SPBRG_ADDR) SPBRG;extern __sfr __at (ADRESL_ADDR) ADRESL;extern __sfr __at (ADCON1_ADDR) ADCON1;extern __sfr __at (EEDATA_ADDR) EEDATA;extern __sfr __at (EEADR_ADDR) EEADR;extern __sfr __at (EEDATH_ADDR) EEDATH;extern __sfr __at (EEADRH_ADDR) EEADRH;extern __sfr __at (EECON1_ADDR) EECON1;extern __sfr __at (EECON2_ADDR) EECON2;//----- STATUS Bits --------------------------------------------------------//----- INTCON Bits --------------------------------------------------------//----- PIR1 Bits ----------------------------------------------------------//----- PIR2 Bits ----------------------------------------------------------//----- T1CON Bits ---------------------------------------------------------//----- T2CON Bits ---------------------------------------------------------//----- SSPCON Bits --------------------------------------------------------//----- CCP1CON Bits -------------------------------------------------------//----- RCSTA Bits ---------------------------------------------------------//----- CCP2CON Bits -------------------------------------------------------//----- ADCON0 Bits --------------------------------------------------------//----- OPTION Bits ----------------------------------------------------//----- PIE1 Bits ----------------------------------------------------------//----- PIE2 Bits ----------------------------------------------------------//----- PCON Bits ----------------------------------------------------------//----- SSPCON2 Bits --------------------------------------------------------//----- SSPSTAT Bits -------------------------------------------------------//----- TXSTA Bits ---------------------------------------------------------//----- ADCON1 Bits --------------------------------------------------------//----- EECON1 Bits --------------------------------------------------------//==========================================================================//// RAM Definition////==========================================================================// __MAXRAM H'1FF'// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'// __BADRAM H'105', H'107'-H'109', H'110'-H'11F'// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F'//==========================================================================//// Configuration Bits////==========================================================================#define _CP_ALL 0x0FCF#define _CP_HALF 0x1FDF#define _CP_UPPER_256 0x2FEF#define _CP_OFF 0x3FFF#define _DEBUG_ON 0x37FF#define _DEBUG_OFF 0x3FFF#define _WRT_ENABLE_ON 0x3FFF#define _WRT_ENABLE_OFF 0x3DFF#define _CPD_ON 0x3EFF#define _CPD_OFF 0x3FFF#define _LVP_ON 0x3FFF #define _LVP_OFF 0x3F7F #define _BODEN_ON 0x3FFF#define _BODEN_OFF 0x3FBF#define _PWRTE_OFF 0x3FFF#define _PWRTE_ON 0x3FF7#define _WDT_ON 0x3FFF#define _WDT_OFF 0x3FFB#define _LP_OSC 0x3FFC#define _XT_OSC 0x3FFD#define _HS_OSC 0x3FFE#define _RC_OSC 0x3FFF// LIST// ----- ADCON0 bits --------------------typedef union { struct { unsigned char ADON:1; unsigned char :1; unsigned char GO:1; unsigned char CHS0:1; unsigned char CHS1:1; unsigned char CHS2:1; unsigned char ADCS0:1; unsigned char ADCS1:1; }; struct { unsigned char :1; unsigned char :1; unsigned char NOT_DONE:1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; }; struct { unsigned char :1; unsigned char :1; unsigned char GO_DONE:1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; };} __ADCON0_bits_t;extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;#define ADON ADCON0_bits.ADON#define GO ADCON0_bits.GO#define NOT_DONE ADCON0_bits.NOT_DONE#define GO_DONE ADCON0_bits.GO_DONE#define CHS0 ADCON0_bits.CHS0#define CHS1 ADCON0_bits.CHS1#define CHS2 ADCON0_bits.CHS2#define ADCS0 ADCON0_bits.ADCS0#define ADCS1 ADCON0_bits.ADCS1// ----- ADCON1 bits --------------------typedef union { struct { unsigned char PCFG0:1; unsigned char PCFG1:1; unsigned char PCFG2:1; unsigned char PCFG3:1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char ADFM:1; };} __ADCON1_bits_t;extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;#define PCFG0 ADCON1_bits.PCFG0#define PCFG1 ADCON1_bits.PCFG1#define PCFG2 ADCON1_bits.PCFG2#define PCFG3 ADCON1_bits.PCFG3#define ADFM ADCON1_bits.ADFM// ----- CCP1CON bits --------------------typedef union { struct { unsigned char CCP1M0:1; unsigned char CCP1M1:1; unsigned char CCP1M2:1; unsigned char CCP1M3:1; unsigned char CCP1Y:1; unsigned char CCP1X:1; unsigned char :1; unsigned char :1; };} __CCP1CON_bits_t;extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;#define CCP1M0 CCP1CON_bits.CCP1M0#define CCP1M1 CCP1CON_bits.CCP1M1#define CCP1M2 CCP1CON_bits.CCP1M2#define CCP1M3 CCP1CON_bits.CCP1M3#define CCP1Y CCP1CON_bits.CCP1Y#define CCP1X CCP1CON_bits.CCP1X// ----- CCP2CON bits --------------------typedef union { struct { unsigned char CCP2M0:1; unsigned char CCP2M1:1; unsigned char CCP2M2:1; unsigned char CCP2M3:1; unsigned char CCP2Y:1; unsigned char CCP2X:1; unsigned char :1; unsigned char :1; };} __CCP2CON_bits_t;extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;#define CCP2M0 CCP2CON_bits.CCP2M0#define CCP2M1 CCP2CON_bits.CCP2M1#define CCP2M2 CCP2CON_bits.CCP2M2#define CCP2M3 CCP2CON_bits.CCP2M3#define CCP2Y CCP2CON_bits.CCP2Y#define CCP2X CCP2CON_bits.CCP2X// ----- EECON1 bits --------------------typedef union { struct { unsigned char RD:1; unsigned char WR:1; unsigned char WREN:1; unsigned char WRERR:1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char EEPGD:1; };} __EECON1_bits_t;extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;#define RD EECON1_bits.RD#define WR EECON1_bits.WR#define WREN EECON1_bits.WREN#define WRERR EECON1_bits.WRERR#define EEPGD EECON1_bits.EEPGD// ----- INTCON bits --------------------typedef union { struct { unsigned char RBIF:1; unsigned char INTF:1; unsigned char T0IF:1; unsigned char RBIE:1; unsigned char INTE:1; unsigned char T0IE:1; unsigned char PEIE:1;?? 快捷鍵說明
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