//// Register Declarations for Microchip 12F629 Processor////// This header file was automatically generated by:////	inc2h.pl V1.7////	Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved////	SDCC is licensed under the GNU Public license (GPL) v2.  Note that//	this license covers the code to the compiler and other executables,//	but explicitly does not cover any code or objects generated by sdcc.//	We have not yet decided on a license for the run time libraries, but//	it will not put any requirements on code linked against it. See:// //	http://www.gnu.org/copyleft/gpl/html////	See http://sdcc.sourceforge.net/ for the latest information on sdcc.//// #ifndef P12F629_H#define P12F629_H//// Register addresses.//#define INDF_ADDR	0x0000#define TMR0_ADDR	0x0001#define PCL_ADDR	0x0002#define STATUS_ADDR	0x0003#define FSR_ADDR	0x0004#define GPIO_ADDR	0x0005#define PCLATH_ADDR	0x000A#define INTCON_ADDR	0x000B#define PIR1_ADDR	0x000C#define TMR1L_ADDR	0x000E#define TMR1H_ADDR	0x000F#define T1CON_ADDR	0x0010#define CMCON_ADDR	0x0019#define OPTION_REG_ADDR	0x0081#define TRISIO_ADDR	0x0085#define PIE1_ADDR	0x008C#define PCON_ADDR	0x008E#define OSCCAL_ADDR	0x0090#define WPU_ADDR	0x0095#define IOCB_ADDR	0x0096#define IOC_ADDR	0x0096#define VRCON_ADDR	0x0099#define EEDATA_ADDR	0x009A#define EEDAT_ADDR	0x009A#define EEADR_ADDR	0x009B#define EECON1_ADDR	0x009C#define EECON2_ADDR	0x009D//// Memory organization.//#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000	// INDF#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000	// TMR0#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000	// PCL#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000	// STATUS#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000	// FSR#pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000	// GPIO#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000	// PCLATH#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000	// INTCON#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000	// PIR1#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000	// TMR1L#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000	// TMR1H#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000	// T1CON#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000	// CMCON#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000	// OPTION_REG#pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000	// TRISIO#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000	// PIE1#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000	// PCON#pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000	// OSCCAL#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000	// WPU#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000	// IOCB#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000	// IOC#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000	// VRCON#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000	// EEDATA#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000	// EEDAT#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000	// EEADR#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000	// EECON1#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000	// EECON2//         LIST// P12F629.INC  Standard Header File, Version 1.04    Microchip Technology, Inc.//         NOLIST// This header file defines configurations, registers, and other useful bits of// information for the PIC12F629 microcontroller.  These names are taken to match // the data sheets as closely as possible.  // Note that the processor must be selected before this file is // included.  The processor may be selected the following ways://       1. Command line switch://               C:\ MPASM MYFILE.ASM /PIC12F629//       2. LIST directive in the source file//               LIST   P=PIC12F629//       3. Processor Type entry in the MPASM full-screen interface//==========================================================================////       Revision History////==========================================================================//1.04	07/01/02 Updated configuration bit names//1.03	05/10/02 Added IOC register//1.02	02/28/02 Updated per datasheet//1.01	01/31/02 Updated per datasheet//1.00   08/24/01 Original//==========================================================================////       Verify Processor////==========================================================================//        IFNDEF __12F629//            MESSG "Processor-header file mismatch.  Verify selected processor."//         ENDIF//==========================================================================////       Register Definitions////==========================================================================#define W                    0x0000#define F                    0x0001//----- Register Files------------------------------------------------------extern __data __at (INDF_ADDR) volatile char      INDF;extern __sfr  __at (TMR0_ADDR)                    TMR0;extern __data __at (PCL_ADDR) volatile char       PCL;extern __sfr  __at (STATUS_ADDR)                  STATUS;extern __sfr  __at (FSR_ADDR)                     FSR;extern __sfr  __at (GPIO_ADDR)                    GPIO;extern __sfr  __at (PCLATH_ADDR)                  PCLATH;extern __sfr  __at (INTCON_ADDR)                  INTCON;extern __sfr  __at (PIR1_ADDR)                    PIR1;extern __sfr  __at (TMR1L_ADDR)                   TMR1L;		extern __sfr  __at (TMR1H_ADDR)                   TMR1H;		extern __sfr  __at (T1CON_ADDR)                   T1CON;		extern __sfr  __at (CMCON_ADDR)                   CMCON;		extern __sfr  __at (OPTION_REG_ADDR)              OPTION_REG;extern __sfr  __at (TRISIO_ADDR)                  TRISIO;extern __sfr  __at (PIE1_ADDR)                    PIE1;extern __sfr  __at (PCON_ADDR)                    PCON;extern __sfr  __at (OSCCAL_ADDR)                  OSCCAL;extern __sfr  __at (WPU_ADDR)                     WPU;extern __sfr  __at (IOCB_ADDR)                    IOCB;extern __sfr  __at (IOC_ADDR)                     IOC;extern __sfr  __at (VRCON_ADDR)                   VRCON;extern __sfr  __at (EEDATA_ADDR)                  EEDATA;	extern __sfr  __at (EEDAT_ADDR)                   EEDAT;	extern __sfr  __at (EEADR_ADDR)                   EEADR;	extern __sfr  __at (EECON1_ADDR)                  EECON1;extern __sfr  __at (EECON2_ADDR)                  EECON2;//----- STATUS Bits --------------------------------------------------------//----- GPIO Bits --------------------------------------------------------//----- INTCON Bits --------------------------------------------------------//----- PIR1 Bits ----------------------------------------------------------//----- T1CON Bits ---------------------------------------------------------//----- CMCON Bits --------------------------------------------------------//----- OPTION Bits --------------------------------------------------------//----- PIE1 Bits ----------------------------------------------------------//----- PCON Bits ----------------------------------------------------------//----- OSCCAL Bits --------------------------------------------------------//----- IOCB Bits --------------------------------------------------------//----- IOC Bits --------------------------------------------------------//----- VRCON Bits ---------------------------------------------------------//----- EECON1 -------------------------------------------------------------//==========================================================================////       RAM Definition////==========================================================================//         __MAXRAM H'FF'//         __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1F', H'60'-H'7F'//         __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'9E'-H'9F', H'E0'-H'FF'//==========================================================================////       Configuration Bits////==========================================================================#define _CPD_ON              0x3EFF#define _CPD_OFF             0x3FFF#define _CP_ON               0x3F7F#define _CP_OFF              0x3FFF#define _BODEN_ON            0x3FFF#define _BODEN_OFF           0x3FBF#define _MCLRE_ON            0x3FFF#define _MCLRE_OFF           0x3FDF#define _PWRTE_OFF           0x3FFF#define _PWRTE_ON            0x3FEF#define _WDT_ON              0x3FFF#define _WDT_OFF             0x3FF7#define _LP_OSC              0x3FF8#define _XT_OSC              0x3FF9#define _HS_OSC              0x3FFA#define _EC_OSC              0x3FFB#define _INTRC_OSC_NOCLKOUT  0x3FFC#define _INTRC_OSC_CLKOUT    0x3FFD#define _EXTRC_OSC_NOCLKOUT  0x3FFE#define _EXTRC_OSC_CLKOUT    0x3FFF//         LIST// ----- CMCON bits --------------------typedef union {  struct {    unsigned char CM0:1;    unsigned char CM1:1;    unsigned char CM2:1;    unsigned char CIS:1;    unsigned char CINV:1;    unsigned char :1;    unsigned char COUT:1;    unsigned char :1;  };} __CMCON_bits_t;extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;#define CM0                  CMCON_bits.CM0#define CM1                  CMCON_bits.CM1#define CM2                  CMCON_bits.CM2#define CIS                  CMCON_bits.CIS#define CINV                 CMCON_bits.CINV#define COUT                 CMCON_bits.COUT// ----- GPIO bits --------------------typedef union {  struct {    unsigned char GP0:1;    unsigned char GP1:1;    unsigned char GP2:1;    unsigned char GP3:1;    unsigned char GP4:1;    unsigned char GP5:1;    unsigned char :1;    unsigned char :1;  };  struct {    unsigned char GPIO0:1;    unsigned char GPIO1:1;    unsigned char GPIO2:1;    unsigned char GPIO3:1;    unsigned char GPIO4:1;    unsigned char GPIO5:1;