/*-------------------------------------------------------------------------   Register Declarations for the Cygnal/SiLabs C8051F04x Processor Range   Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl   This library is free software; you can redistribute it and/or   modify it under the terms of the GNU Lesser General Public   License as published by the Free Software Foundation; either   version 2.1 of the License, or (at your option) any later version.   This library is distributed in the hope that it will be useful,   but WITHOUT ANY WARRANTY; without even the implied warranty of   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU   Lesser General Public License for more details.   You should have received a copy of the GNU Lesser General Public   License along with this library; if not, write to the Free Software   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA-------------------------------------------------------------------------*/#ifndef C8051F040_H#define C8051F040_H/*  BYTE Registers  *//*  All Pages */__sfr __at 0x80 P0       ;  /* PORT 0                                        */__sfr __at 0x81 SP       ;  /* STACK POINTER                                 */__sfr __at 0x82 DPL      ;  /* DATA POINTER - LOW BYTE                       */__sfr __at 0x83 DPH      ;  /* DATA POINTER - HIGH BYTE                      */__sfr __at 0x84 SFRPAGE  ;  /* SFR PAGE SELECT                               */__sfr __at 0x85 SFRNEXT  ;  /* SFR STACK NEXT PAGE                           */__sfr __at 0x86 SFRLAST  ;  /* SFR STACK LAST PAGE                           */__sfr __at 0x87 PCON     ;  /* POWER CONTROL                                 */__sfr __at 0x90 P1       ;  /* PORT 1                                        */__sfr __at 0xA0 P2       ;  /* PORT 2                                        */__sfr __at 0xA8 IE       ;  /* INTERRUPT ENABLE                              */__sfr __at 0xB0 P3       ;  /* PORT 3                                        */__sfr __at 0xB8 IP       ;  /* INTERRUPT PRIORITY                            */__sfr __at 0xD0 PSW      ;  /* PROGRAM STATUS WORD                           */__sfr __at 0xE0 ACC      ;  /* ACCUMULATOR                                   */__sfr __at 0xE6 EIE1     ;  /* EXTERNAL INTERRUPT ENABLE 1                   */__sfr __at 0xE7 EIE2     ;  /* EXTERNAL INTERRUPT ENABLE 2                   */__sfr __at 0xF0 B        ;  /* B REGISTER                                    */__sfr __at 0xF6 EIP1     ;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 1        */__sfr __at 0xF7 EIP2     ;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 2        */__sfr __at 0xFF WDTCN    ;  /* WATCHDOG TIMER CONTROL                        *//*  Page 0x00 */__sfr __at 0x88 TCON     ;  /* TIMER CONTROL                                 */__sfr __at 0x89 TMOD     ;  /* TIMER MODE                                    */__sfr __at 0x8A TL0      ;  /* TIMER 0 - LOW BYTE                            */__sfr __at 0x8B TL1      ;  /* TIMER 1 - LOW BYTE                            */__sfr __at 0x8C TH0      ;  /* TIMER 0 - HIGH BYTE                           */__sfr __at 0x8D TH1      ;  /* TIMER 1 - HIGH BYTE                           */__sfr __at 0x8E CKCON    ;  /* TIMER 0/1 CLOCK CONTROL                       */__sfr __at 0x8F PSCTL    ;  /* FLASH WRITE/ERASE CONTROL                     */__sfr __at 0x91 SSTA0    ;  /* UART 0 STATUS                                 */__sfr __at 0x98 SCON0    ;  /* UART 0 CONTROL                                */__sfr __at 0x98 SCON     ;  /* UART 0 CONTROL                                */__sfr __at 0x99 SBUF0    ;  /* UART 0 BUFFER                                 */__sfr __at 0x99 SBUF     ;  /* UART 0 BUFFER                                 */__sfr __at 0x9A SPI0CFG  ;  /* SPI 0 CONFIGURATION                           */__sfr __at 0x9B SPI0DAT  ;  /* SPI 0 DATA                                    */__sfr __at 0x9D SPI0CKR  ;  /* SPI 0 CLOCK RATE CONTROL                      */__sfr __at 0xA1 EMI0TC   ;  /* EMIF TIMING CONTROL                           */__sfr __at 0xA2 EMI0CN   ;  /* EMIF CONTROL                                  */__sfr __at 0xA2 _XPAGE   ;  /* XDATA/PDATA PAGE                              */__sfr __at 0xA3 EMI0CF   ;  /* EMIF CONFIGURATION                            */__sfr __at 0xA9 SADDR0   ;  /* UART 0 SLAVE ADDRESS                          */__sfr __at 0xB7 FLSCL    ;  /* FLASH SCALE                                   */__sfr __at 0xB9 SADEN0   ;  /* UART 0 SLAVE ADDRESS MASK                     */__sfr __at 0xBA AMX0CF   ;  /* ADC 0 MUX CONFIGURATION                       */__sfr __at 0xBB AMX0SL   ;  /* ADC 0 MUX CHANNEL SELECTION                   */__sfr __at 0xBC ADC0CF   ;  /* ADC 0 CONFIGURATION                           */__sfr __at 0xBD AMX0PRT  ;  /* ADC 0 PORT 3 I/O PIN SELECT                   */__sfr __at 0xBE ADC0L    ;  /* ADC 0 DATA - LOW BYTE                         */__sfr __at 0xBF ADC0H    ;  /* ADC 0 DATA - HIGH BYTE                        */__sfr __at 0xC0 SMB0CN   ;  /* SMBUS 0 CONTROL                               */__sfr __at 0xC1 SMB0STA  ;  /* SMBUS 0 STATUS                                */__sfr __at 0xC2 SMB0DAT  ;  /* SMBUS 0 DATA                                  */__sfr __at 0xC3 SMB0ADR  ;  /* SMBUS 0 SLAVE ADDRESS                         */__sfr __at 0xC4 ADC0GTL  ;  /* ADC 0 GREATER-THAN REGISTER - LOW BYTE        */__sfr __at 0xC5 ADC0GTH  ;  /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE       */__sfr __at 0xC6 ADC0LTL  ;  /* ADC 0 LESS-THAN REGISTER - LOW BYTE           */__sfr __at 0xC7 ADC0LTH  ;  /* ADC 0 LESS-THAN REGISTER - HIGH BYTE          */__sfr __at 0xC8 TMR2CN   ;  /* TIMER 2 CONTROL                               */__sfr __at 0xC9 TMR2CF   ;  /* TIMER 2 CONFIGURATION                         */__sfr __at 0xCA RCAP2L   ;  /* TIMER 2 CAPTURE REGISTER - LOW BYTE           */__sfr __at 0xCB RCAP2H   ;  /* TIMER 2 CAPTURE REGISTER - HIGH BYTE          */__sfr __at 0xCC TMR2L    ;  /* TIMER 2 - LOW BYTE                            */__sfr __at 0xCC TL2      ;  /* TIMER 2 - LOW BYTE                            */__sfr __at 0xCD TMR2H    ;  /* TIMER 2 - HIGH BYTE                           */__sfr __at 0xCD TH2      ;  /* TIMER 2 - HIGH BYTE                           */__sfr __at 0xCF SMB0CR   ;  /* SMBUS 0 CLOCK RATE                            */__sfr __at 0xD1 REF0CN   ;  /* VOLTAGE REFERENCE 0 CONTROL                   */__sfr __at 0xD2 DAC0L    ;  /* DAC 0 REGISTER - LOW BYTE                     */__sfr __at 0xD3 DAC0H    ;  /* DAC 0 REGISTER - HIGH BYTE                    */__sfr __at 0xD4 DAC0CN   ;  /* DAC 0 CONTROL                                 */__sfr __at 0xD6 HVA0CN   ;  /* HIGH VOLTAGE DIFFERENTIAL AMP CONTROL         */__sfr __at 0xD8 PCA0CN   ;  /* PCA 0 COUNTER CONTROL                         */__sfr __at 0xD9 PCA0MD   ;  /* PCA 0 COUNTER MODE                            */__sfr __at 0xDA PCA0CPM0 ;  /* PCA 0 MODULE 0 CONTROL                        */__sfr __at 0xDB PCA0CPM1 ;  /* PCA 0 MODULE 1 CONTROL                        */__sfr __at 0xDC PCA0CPM2 ;  /* PCA 0 MODULE 2 CONTROL                        */__sfr __at 0xDD PCA0CPM3 ;  /* PCA 0 MODULE 3 CONTROL                        */__sfr __at 0xDE PCA0CPM4 ;  /* PCA 0 MODULE 4 CONTROL                        */__sfr __at 0xDF PCA0CPM5 ;  /* PCA 0 MODULE 5 CONTROL                        */__sfr __at 0xE1 PCA0CPL5 ;  /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE     */__sfr __at 0xE2 PCA0CPH5 ;  /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE    */__sfr __at 0xE8 ADC0CN   ;  /* ADC 0 CONTROL                                 */__sfr __at 0xE9 PCA0CPL2 ;  /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE     */__sfr __at 0xEA PCA0CPH2 ;  /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE    */__sfr __at 0xEB PCA0CPL3 ;  /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE     */__sfr __at 0xEC PCA0CPH3 ;  /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE    */__sfr __at 0xED PCA0CPL4 ;  /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE     */__sfr __at 0xEE PCA0CPH4 ;  /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE    */__sfr __at 0xEF RSTSRC   ;  /* RESET SOURCE                                  */__sfr __at 0xF8 SPI0CN   ;  /* SPI 0 CONTROL                                 */__sfr __at 0xF9 PCA0L    ;  /* PCA 0 TIMER - LOW BYTE                        */__sfr __at 0xFA PCA0H    ;  /* PCA 0 TIMER - HIGH BYTE                       */__sfr __at 0xFB PCA0CPL0 ;  /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE     */__sfr __at 0xFC PCA0CPH0 ;  /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE    */__sfr __at 0xFD PCA0CPL1 ;  /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE     */__sfr __at 0xFE PCA0CPH1 ;  /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE    *//*  Page 0x01 */__sfr __at 0x88 CPT0CN   ;  /* COMPARATOR 0 CONTROL                          */__sfr __at 0x89 CPT0MD   ;  /* COMPARATOR 0 CONFIGURATION                    */__sfr __at 0x98 SCON1    ;  /* UART 1 CONTROL                                */__sfr __at 0x99 SBUF1    ;  /* UART 1 BUFFER                                 */__sfr __at 0xC0 CAN0STA  ;  /* CAN 0 STATUS                                  */__sfr __at 0xC8 TMR3CN   ;  /* TIMER 3 CONTROL                               */__sfr __at 0xC9 TMR3CF   ;  /* TIMER 3 CONFIGURATION                         */__sfr __at 0xCA RCAP3L   ;  /* TIMER 3 CAPTURE REGISTER - LOW BYTE           */__sfr __at 0xCB RCAP3H   ;  /* TIMER 3 CAPTURE REGISTER - HIGH BYTE          */__sfr __at 0xCC TMR3L    ;  /* TIMER 3 - LOW BYTE                            */__sfr __at 0xCD TMR3H    ;  /* TIMER 3 - HIGH BYTE                           */__sfr __at 0xD2 DAC1L    ;  /* DAC 1 REGISTER - LOW BYTE                     */__sfr __at 0xD3 DAC1H    ;  /* DAC 1 REGISTER - HIGH BYTE                    */__sfr __at 0xD4 DAC1CN   ;  /* DAC 1 CONTROL                                 */__sfr __at 0xD8 CAN0DATL ;  /* CAN 0 DATA REGISTER LOW                       */__sfr __at 0xD9 CAN0DATH ;  /* CAN 0 DATA REGISTER HIGH                      */__sfr __at 0xDA CAN0ADR  ;  /* CAN 0 ADDRESS                                 */__sfr __at 0xDB CAN0TST  ;  /* CAN 0 TEST REGISTER                           */__sfr __at 0xF8 CAN0CN   ;  /* CAN 0 CONTROL                                 *//*  Page 0x02 */__sfr __at 0x88 CPT1CN   ;  /* COMPARATOR 1 CONTROL                          */__sfr __at 0x89 CPT1MD   ;  /* COMPARATOR 1 CONFIGURATION                    */__sfr __at 0xBA AMX2CF   ;  /* ADC 2 MUX CONFIGURATION                       */__sfr __at 0xBB AMX2SL   ;  /* ADC 2 MUX CHANNEL SELECTION                   */__sfr __at 0xBC ADC2CF   ;  /* ADC 2 CONFIGURATION                           */__sfr __at 0xBE ADC2     ;  /* ADC 2 DATA                                    */__sfr __at 0xC4 ADC2GT   ;  /* ADC 2 GREATER-THAN REGISTER                   */__sfr __at 0xC6 ADC2LT   ;  /* ADC 2 LESS-THAN REGISTER                      */__sfr __at 0xC8 TMR4CN   ;  /* TIMER 4 CONTROL                               */__sfr __at 0xC9 TMR4CF   ;  /* TIMER 4 CONFIGURATION                         */__sfr __at 0xCA RCAP4L   ;  /* TIMER 4 CAPTURE REGISTER - LOW BYTE           */__sfr __at 0xCB RCAP4H   ;  /* TIMER 4 CAPTURE REGISTER - HIGH BYTE          */__sfr __at 0xCC TMR4L    ;  /* TIMER 4 - LOW BYTE                            */__sfr __at 0xCD TMR4H    ;  /* TIMER 4 - HIGH BYTE                           */__sfr __at 0xE8 ADC2CN   ;  /* ADC 2 CONTROL                                 *//*  Page 0x03 */__sfr __at 0x88 CPT2CN   ;  /* COMPARATOR 2 CONTROL                          */__sfr __at 0x89 CPT2MD   ;  /* COMPARATOR 2 CONFIGURATION                    *//*  Page 0x0F */__sfr __at 0x8A OSCICN   ;  /* INTERNAL OSCILLATOR CONTROL                   */__sfr __at 0x8B OSCICL   ;  /* INTERNAL OSCILLATOR CALIBRATION               */__sfr __at 0x8C OSCXCN   ;  /* EXTERNAL OSCILLATOR CONTROL                   */__sfr __at 0x96 SFRPGCN  ;  /* SFR PAGE CONTROL                              */__sfr __at 0x97 CLKSEL   ;  /* SYSTEM CLOCK SELECT                           */__sfr __at 0x9C P4MDOUT  ;  /* PORT 4 OUTPUT MODE                            */__sfr __at 0x9D P5MDOUT  ;  /* PORT 5 OUTPUT MODE                            */__sfr __at 0x9E P6MDOUT  ;  /* PORT 6 OUTPUT MODE                            */__sfr __at 0x9F P7MDOUT  ;  /* PORT 7 OUTPUT MODE                            */__sfr __at 0xA4 P0MDOUT  ;  /* PORT 0 OUTPUT MODE                            */__sfr __at 0xA5 P1MDOUT  ;  /* PORT 1 OUTPUT MODE                            */__sfr __at 0xA6 P2MDOUT  ;  /* PORT 2 OUTPUT MODE CONFIGURATION              */__sfr __at 0xA7 P3MDOUT  ;  /* PORT 3 OUTPUT MODE CONFIGURATION              */__sfr __at 0xAD P1MDIN   ;  /* PORT 1 INPUT MODE                             */__sfr __at 0xAE P2MDIN   ;  /* PORT 2 INPUT MODE                             */__sfr __at 0xAF P3MDIN   ;  /* PORT 3 INPUT MODE                             */__sfr __at 0xB7 FLACL    ;  /* FLASH ACCESS LIMIT                            */__sfr __at 0xC8 P4       ;  /* PORT 4                                        */__sfr __at 0xD8 P5       ;  /* PORT 5                                        */__sfr __at 0xE1 XBR0     ;  /* CROSSBAR CONFIGURATION REGISTER 0             */__sfr __at 0xE2 XBR1     ;  /* CROSSBAR CONFIGURATION REGISTER 1             */__sfr __at 0xE3 XBR2     ;  /* CROSSBAR CONFIGURATION REGISTER 2             */__sfr __at 0xE4 XBR3     ;  /* CROSSBAR CONFIGURATION REGISTER 3             */__sfr __at 0xE8 P6       ;  /* PORT 6                                        */__sfr __at 0xF8 P7       ;  /* PORT 7                                        *//*  BIT Registers  *//*  P0  0x80 */__sbit __at 0x80 P0_0    ;__sbit __at 0x81 P0_1    ;__sbit __at 0x82 P0_2    ;__sbit __at 0x83 P0_3    ;__sbit __at 0x84 P0_4    ;__sbit __at 0x85 P0_5    ;__sbit __at 0x86 P0_6    ;__sbit __at 0x87 P0_7    ;/*  TCON  0x88 */__sbit __at 0x88 IT0     ;  /* EXT. INTERRUPT 0 TYPE                         */__sbit __at 0x89 IE0     ;  /* EXT. INTERRUPT 0 EDGE FLAG                    */__sbit __at 0x8A IT1     ;  /* EXT. INTERRUPT 1 TYPE                         */__sbit __at 0x8B IE1     ;  /* EXT. INTERRUPT 1 EDGE FLAG                    */__sbit __at 0x8C TR0     ;  /* TIMER 0 ON/OFF CONTROL                        */__sbit __at 0x8D TF0     ;  /* TIMER 0 OVERFLOW FLAG                         */__sbit __at 0x8E TR1     ;  /* TIMER 1 ON/OFF CONTROL                        */__sbit __at 0x8F TF1     ;  /* TIMER 1 OVERFLOW FLAG                         *//*  CPT0CN  0x88 */__sbit __at 0x88 CP0HYN0 ;  /* COMPARATOR 0 NEGATIVE HYSTERESIS 0            */__sbit __at 0x89 CP0HYN1 ;  /* COMPARATOR 0 NEGATIVE HYSTERESIS 1            */__sbit __at 0x8A CP0HYP0 ;  /* COMPARATOR 0 POSITIVE HYSTERESIS 0            */__sbit __at 0x8B CP0HYP1 ;  /* COMPARATOR 0 POSITIVE HYSTERESIS 1            */__sbit __at 0x8C CP0FIF  ;  /* COMPARATOR 0 FALLING EDGE INTERRUPT           */__sbit __at 0x8D CP0RIF  ;  /* COMPARATOR 0 RISING EDGE INTERRUPT            */__sbit __at 0x8E CP0OUT  ;  /* COMPARATOR 0 OUTPUT                           */__sbit __at 0x8F CP0EN   ;  /* COMPARATOR 0 ENABLE                           *//*  CPT1CN  0x88 */__sbit __at 0x88 CP1HYN0 ;  /* COMPARATOR 1 NEGATIVE HYSTERESIS 0            */__sbit __at 0x89 CP1HYN1 ;  /* COMPARATOR 1 NEGATIVE HYSTERESIS 1            */__sbit __at 0x8A CP1HYP0 ;  /* COMPARATOR 1 POSITIVE HYSTERESIS 0            */__sbit __at 0x8B CP1HYP1 ;  /* COMPARATOR 1 POSITIVE HYSTERESIS 1            */__sbit __at 0x8C CP1FIF  ;  /* COMPARATOR 1 FALLING EDGE INTERRUPT           */__sbit __at 0x8D CP1RIF  ;  /* COMPARATOR 1 RISING EDGE INTERRUPT            */__sbit __at 0x8E CP1OUT  ;  /* COMPARATOR 1 OUTPUT                           */__sbit __at 0x8F CP1EN   ;  /* COMPARATOR 1 ENABLE                           *//*  CPT2CN  0x88 */__sbit __at 0x88 CP2HYN0 ;  /* COMPARATOR 2 NEGATIVE HYSTERESIS 0            */__sbit __at 0x89 CP2HYN1 ;  /* COMPARATOR 2 NEGATIVE HYSTERESIS 1            */__sbit __at 0x8A CP2HYP0 ;  /* COMPARATOR 2 POSITIVE HYSTERESIS 0            */__sbit __at 0x8B CP2HYP1 ;  /* COMPARATOR 2 POSITIVE HYSTERESIS 1            */__sbit __at 0x8C CP2FIF  ;  /* COMPARATOR 2 FALLING EDGE INTERRUPT           */__sbit __at 0x8D CP2RIF  ;  /* COMPARATOR 2 RISING EDGE INTERRUPT            */__sbit __at 0x8E CP2OUT  ;  /* COMPARATOR 2 OUTPUT                           */__sbit __at 0x8F CP2EN   ;  /* COMPARATOR 2 ENABLE                           *//*  P1  0x90 */__sbit __at 0x90 P1_0    ;