?? c8051f020.h
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/*------------------------------------------------------------------------- Register Declarations for the Cygnal/SiLabs C8051F02x Processor Range Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA-------------------------------------------------------------------------*/#ifndef C8051F020_H#define C8051F020_H/* BYTE Registers */__sfr __at (0x80) P0 ; /* PORT 0 */__sfr __at (0x81) SP ; /* STACK POINTER */__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */__sfr __at (0x84) P4 ; /* PORT 4 */__sfr __at (0x85) P5 ; /* PORT 5 */__sfr __at (0x86) P6 ; /* PORT 6 */__sfr __at (0x87) PCON ; /* POWER CONTROL */__sfr __at (0x88) TCON ; /* TIMER CONTROL */__sfr __at (0x89) TMOD ; /* TIMER MODE */__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */__sfr __at (0x90) P1 ; /* PORT 1 */__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */__sfr __at (0x92) TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */__sfr __at (0x93) TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */__sfr __at (0x96) P7 ; /* PORT 7 */__sfr __at (0x98) SCON ; /* UART0 CONTROL */__sfr __at (0x98) SCON0 ; /* UART0 CONTROL */__sfr __at (0x99) SBUF ; /* UART0 BUFFER */__sfr __at (0x99) SBUF0 ; /* UART0 BUFFER */__sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */__sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */__sfr __at (0x9C) ADC1 ; /* ADC 1 DATA */__sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */__sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 CONTROL */__sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 CONTROL */__sfr __at (0xA0) P2 ; /* PORT 2 */__sfr __at (0xA1) EMI0TC ; /* External Memory Timing Control */__sfr __at (0xA3) EMI0CF ; /* EMIF CONFIGURATION */__sfr __at (0xA4) PRT0CF ; /* PORT 0 CONFIGURATION */__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */__sfr __at (0xA5) PRT1CF ; /* PORT 1 CONFIGURATION */__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */__sfr __at (0xA6) PRT2CF ; /* PORT 2 CONFIGURATION */__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */__sfr __at (0xA7) PRT3CF ; /* PORT 3 CONFIGURATION */__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */__sfr __at (0xA9) SADDR0 ; /* UART0 Slave Address */__sfr __at (0xAA) ADC1CN ; /* ADC 1 CONTROL */__sfr __at (0xAB) ADC1CF ; /* ADC 1 CONFIGURATION */__sfr __at (0xAC) AMX1SL ; /* ADC 1 MUX CHANNEL SELECTION */__sfr __at (0xAD) P3IF ; /* PORT 3 EXTERNAL INTERRUPT FLAGS */__sfr __at (0xAE) SADEN1 ; /* UART1 Slave Address Enable */__sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */__sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */__sfr __at (0xB0) P3 ; /* PORT 3 */__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */__sfr __at (0xB5) P74OUT ; /* PORT 4 THROUGH 7 OUTPUT MODE CONFIGURATION */__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */__sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */__sfr __at (0xB9) SADEN0 ; /* UART0 Slave Address Enable */__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */__sfr __at (0xBD) P1MDIN ; /* PORT 1 Input Mode */__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */__sfr __at (0xC9) T4CON ; /* TIMER 4 CONTROL */__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */__sfr __at (0xD2) DAC0L ; /* DAC 0 REGISTER - LOW BYTE */__sfr __at (0xD3) DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */__sfr __at (0xD4) DAC0CN ; /* DAC 0 CONTROL */__sfr __at (0xD5) DAC1L ; /* DAC 1 REGISTER - LOW BYTE */__sfr __at (0xD6) DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */__sfr __at (0xD7) DAC1CN ; /* DAC 1 CONTROL */__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */__sfr __at (0xDA) PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */__sfr __at (0xDB) PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */__sfr __at (0xDC) PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */__sfr __at (0xDD) PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */__sfr __at (0xDE) PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */__sfr __at (0xE0) ACC ; /* ACCUMULATOR */__sfr __at (0xE1) XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */__sfr __at (0xE2) XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */__sfr __at (0xE3) XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */__sfr __at (0xE4) RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */__sfr __at (0xE5) RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */__sfr __at (0xE9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */__sfr __at (0xEA) PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */__sfr __at (0xEB) PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */__sfr __at (0xEC) PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */__sfr __at (0xED) PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */__sfr __at (0xEE) PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */__sfr __at (0xF0) B ; /* B REGISTER */__sfr __at (0xF1) SCON1 ; /* UART1 CONTROL */__sfr __at (0xF2) SBUF1 ; /* UART1 DATA */__sfr __at (0xF3) SADDR1 ; /* UART1 Slave Address */__sfr __at (0xF4) TL4 ; /* TIMER 4 DATA - LOW BYTE */__sfr __at (0xF5) TH4 ; /* TIMER 4 DATA - HIGH BYTE */__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */__sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */__sfr __at (0xF9) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */__sfr __at (0xFA) PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */__sfr __at (0xFB) PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */__sfr __at (0xFC) PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */__sfr __at (0xFD) PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */__sfr __at (0xFE) PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL *//* WORD/DWORD Registers */__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */__sfr16 __at (0xF5F4) TMR4 ; /* TIMER 4 COUNTER */__sfr16 __at (0xE5E4) RCAP4 ; /* TIMER 4 CAPTURE REGISTER WORD */__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */__sfr16 __at (0xD3D2) DAC0 ; /* DAC 0 REGISTER WORD */__sfr16 __at (0xD6D5) DAC1 ; /* DAC 1 REGISTER WORD */__sfr16 __at (0xF9E9) PCA0 ; /* PCA COUNTER */__sfr16 __at (0xFAEA) PCA0CP0 ; /* PCA CAPTURE 0 WORD */__sfr16 __at (0xFBEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */__sfr16 __at (0xFCEC) PCA0CP2 ; /* PCA CAPTURE 2 WORD */__sfr16 __at (0xFDED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */__sfr16 __at (0xFEEE) PCA0CP4 ; /* PCA CAPTURE 4 WORD *//* BIT Registers *//* P0 0x80 */__sbit __at (0x80) P0_0 ;__sbit __at (0x81) P0_1 ;__sbit __at (0x82) P0_2 ;?? 快捷鍵說明
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