/* * Simulator of microcontrollers (arith_inst.cc) * * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. *  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu * *//* This file is part of microcontroller simulator: ucsim.UCSIM is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2 of the License, or(at your option) any later version.UCSIM is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with UCSIM; see the file COPYING.  If not, write to the FreeSoftware Foundation, 59 Temple Place - Suite 330, Boston, MA02111-1307, USA. *//*@1@*/#include "avrcl.h"#include "regsavr.h"/* * Compare with Immediate * CPI Rd,K 16<=d<=31, 0<=K<=255 * 0011 KKKK dddd KKKK *____________________________________________________________________________ */intcl_avr::cpi_Rd_K(t_mem code){  t_addr d;  t_mem D, K, result, res;  d= 16+(code&0xf0)>>4;  K= (code&0xf) | ((code&0xf00)>>8);  D= ram->read(d);  if (K & 0x80)    K|= ~0xff;  if (D & 0x80)    D|= ~0xff;  t_mem sreg= ram->get(SREG);  result= (signed)D-(signed)K;  res= result & 0xff;    sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C|BIT_Z);  if (0x08 & (((~D)&K) | (K&res) | (res&(~D))))    sreg|= BIT_H;  int n= 0, v= 0;  if (0x80 & ((D&(~K)&(~res)) | ((~D)&K&res)))    {      sreg|= BIT_V;      v= 1;    }  if (res & 0x80)    {      sreg|= BIT_N;      n= 1;    }  if ((n ^ v) & 1)    sreg|= BIT_S;  if (!res)    sreg|= BIT_Z;  if (0x80 & (((~D)&K) | (K&res) | (res&(~D))))    sreg|= BIT_C;  ram->set(SREG, sreg);  return(resGO);}/* * Substract Immediate with Carry * SBCI Rd,K 16<=d<=31, 0<=K<=255 * 0100 KKKK dddd KKKK *____________________________________________________________________________ */intcl_avr::sbci_Rd_K(t_mem code){  t_addr d;  t_mem D, K, result, res;  d= 16+(code&0xf0)>>4;  K= (code&0xf) | ((code&0xf00)>>8);  D= ram->read(d);  if (K & 0x80)    K|= ~0xff;  if (D & 0x80)    D|= ~0xff;  t_mem sreg= ram->get(SREG);  result= (signed)D-(signed)K-(sreg&BIT_C)?1:0;  res= result & 0xff;  ram->write(d, res);    sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C);  if (0x08 & (((~D)&K) | (K&res) | (res&(~D))))    sreg|= BIT_H;  int n= 0, v= 0;  if (0x80 & ((D&(~K)&(~res)) | ((~D)&K&res)))    {      sreg|= BIT_V;      v= 1;    }  if (res & 0x80)    {      sreg|= BIT_N;      n= 1;    }  if ((n ^ v) & 1)    sreg|= BIT_S;  if (res)    sreg&= ~BIT_Z;  if (0x80 & (((~D)&K) | (K&res) | (res&(~D))))    sreg|= BIT_C;  ram->set(SREG, sreg);  return(resGO);}/* * Substract Immediate * SUBI Rd,K 16<=d<=31, 0<=K<=255 * 0101 KKKK dddd KKKK *____________________________________________________________________________ */intcl_avr::subi_Rd_K(t_mem code){  t_addr d;  t_mem D, K, result, res;  d= 16+(code&0xf0)>>4;  K= (code&0xf) | ((code&0xf00)>>8);  D= ram->read(d);  if (K & 0x80)    K|= ~0xff;  if (D & 0x80)    D|= ~0xff;  result= (signed)D-(signed)K;  res= result & 0xff;  ram->write(d, res);    t_mem sreg= ram->get(SREG) & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);  if (0x08 & (((~D)&K) | (K&res) | (res&(~D))))    sreg|= BIT_H;  int n= 0, v= 0;  if (0x80 & ((D&(~K)&(~res)) | ((~D)&K&res)))    {      sreg|= BIT_V;      v= 1;    }  if (res & 0x80)    {      sreg|= BIT_N;      n= 1;    }  if ((n ^ v) & 1)    sreg|= BIT_S;  if (!res)    sreg|= BIT_Z;  if (0x80 & (((~D)&K) | (K&res) | (res&(~D))))    sreg|= BIT_C;  ram->set(SREG, sreg);  return(resGO);}intcl_avr::muls_Rd_Rr(t_mem code){  return(resGO);}intcl_avr::mulsu_Rd_Rr(t_mem code){  return(resGO);}intcl_avr::fmul_Rd_Rr(t_mem code){  return(resGO);}intcl_avr::fmuls_Rd_Rr(t_mem code){  return(resGO);}intcl_avr::fmulsu_Rd_Rr(t_mem code){  return(resGO);}/* * Compare with Carry * CPC Rd,Rr 0<=d<=31, 0<=r<=31 * 0000 01rd dddd rrrr *____________________________________________________________________________ */intcl_avr::cpc_Rd_Rr(t_mem code){  t_addr r, d;  t_mem R, D, result, res;  d= (code&0x1f0)>>4;  r= ((code&0x200)>>5)|(code&0xf);  R= ram->read(r);  D= ram->read(d);  if (R & 0x80)    R|= ~0xff;  if (D & 0x80)    D|= ~0xff;  t_mem sreg= ram->get(SREG);  result= (signed)D-(signed)R-(sreg&BIT_C)?1:0;  res= result & 0xff;    sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C);  if (0x08 & (((~D)&R) | (R&res) | (res&(~D))))    sreg|= BIT_H;  int n= 0, v= 0;  if (0x80 & ((D&(~R)&(~res)) | ((~D)&R&res)))    {      sreg|= BIT_V;      v= 1;    }  if (res & 0x80)    {      sreg|= BIT_N;      n= 1;    }  if ((n ^ v) & 1)    sreg|= BIT_S;  if (res)    sreg&= ~BIT_Z;  if (0x80 & (((~D)&R) | (R&res) | (res&(~D))))    sreg|= BIT_C;  ram->set(SREG, sreg);  return(resGO);}/* * Substract with Carry * SBC Rd,Rr 0<=d<=31, 0<=r<=31 * 0000 10rd dddd rrrr *____________________________________________________________________________ */intcl_avr::sbc_Rd_Rr(t_mem code){  t_addr r, d;  t_mem R, D, result, res;  d= (code&0x1f0)>>4;  r= ((code&0x200)>>5)|(code&0xf);  R= ram->read(r);  D= ram->read(d);  if (R & 0x80)    R|= ~0xff;  if (D & 0x80)    D|= ~0xff;  t_mem sreg= ram->get(SREG);  result= (signed)D-(signed)R-(sreg&BIT_C)?1:0;  res= result & 0xff;  ram->write(d, res);    sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C);  if (0x08 & (((~D)&R) | (R&res) | (res&(~D))))    sreg|= BIT_H;  int n= 0, v= 0;  if (0x80 & ((D&(~R)&(~res)) | ((~D)&R&res)))    {      sreg|= BIT_V;      v= 1;    }  if (res & 0x80)    {      sreg|= BIT_N;      n= 1;    }  if ((n ^ v) & 1)    sreg|= BIT_S;  if (res)    sreg&= ~BIT_Z;  if (0x80 & (((~D)&R) | (R&res) | (res&(~D))))    sreg|= BIT_C;  ram->set(SREG, sreg);  return(resGO);}/* * Add without Carry * ADD Rd,Rr 0<=d<=31, 0<=r<=31 * 0000 11rd dddd rrrr *____________________________________________________________________________ */intcl_avr::add_Rd_Rr(t_mem code){  t_addr r, d;  t_mem R, D, result, res;  d= (code&0x1f0)>>4;  r= ((code&0x200)>>5)|(code&0xf);  R= ram->read(r);  D= ram->read(d);  result= D+R;  res= result & 0xff;  ram->write(d, res);    t_mem sreg= ram->get(SREG);  if (!res)    sreg|= BIT_Z;  else    sreg&= ~BIT_Z;  if (((D&R&~res)&0x80) ||      ((~D&~R&res)&0x80))    sreg|= (BIT_V|BIT_S);  else    sreg&= ~(BIT_V|BIT_S);  if (res & 0x80)    {      sreg|= BIT_N;      sreg^= BIT_S;    }  else    sreg&= ~BIT_N;  if (result & ~0xff)    sreg|= BIT_C;  else    sreg&= ~BIT_C;  if ((R&0xf) + (D&0xf) > 15)    sreg|= BIT_H;  else    sreg&= ~BIT_H;  ram->set(SREG, sreg);  return(resGO);}/* * Compare * CP Rd,Rr 0<=d<=31, 0<=r<=31 * 0001 01rd dddd rrrr *____________________________________________________________________________ */intcl_avr::cp_Rd_Rr(t_mem code){  t_addr r, d;  t_mem R, D, result, res;  d= (code&0x1f0)>>4;  r= ((code&0x200)>>5)|(code&0xf);  R= ram->read(r);  D= ram->read(d);  if (R & 0x80)    R|= ~0xff;  if (D & 0x80)    D|= ~0xff;  result= (signed)D-(signed)R;  res= result & 0xff;    t_mem sreg= ram->get(SREG) & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);  if (0x08 & (((~D)&R) | (R&res) | (res&(~D))))    sreg|= BIT_H;  int n= 0, v= 0;  if (0x80 & ((D&(~R)&(~res)) | ((~D)&R&res)))    {      sreg|= BIT_V;      v= 1;    }  if (res & 0x80)    {      sreg|= BIT_N;      n= 1;    }  if ((n ^ v) & 1)    sreg|= BIT_S;  if (!res)    sreg|= BIT_Z;  if (0x80 & (((~D)&R) | (R&res) | (res&(~D))))    sreg|= BIT_C;  ram->set(SREG, sreg);  return(resGO);}/* * Substract without Carry * SUB Rd,Rr 0<=d<=31, 0<=r<=31 * 0001 10rd dddd rrrr *____________________________________________________________________________ */intcl_avr::sub_Rd_Rr(t_mem code){  t_addr r, d;  t_mem R, D, result, res;  d= (code&0x1f0)>>4;  r= ((code&0x200)>>5)|(code&0xf);  R= ram->read(r);  D= ram->read(d);  if (R & 0x80)    R|= ~0xff;  if (D & 0x80)    D|= ~0xff;  result= (signed)D-(signed)R;  res= result & 0xff;  ram->write(d, res);    t_mem sreg= ram->get(SREG) & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);  if (0x08 & (((~D)&R) | (R&res) | (res&(~D))))    sreg|= BIT_H;  int n= 0, v= 0;  if (0x80 & ((D&(~R)&(~res)) | ((~D)&R&res)))    {      sreg|= BIT_V;      v= 1;    }  if (res & 0x80)    {      sreg|= BIT_N;      n= 1;    }  if ((n ^ v) & 1)    sreg|= BIT_S;  if (!res)    sreg|= BIT_Z;  if (0x80 & (((~D)&R) | (R&res) | (res&(~D))))    sreg|= BIT_C;  ram->set(SREG, sreg);  return(resGO);}/* * Add with Carry * ADC Rd,Rr 0<=d<=31, 0<=r<=31 * 0001 11rd dddd rrrr *____________________________________________________________________________ */intcl_avr::adc_Rd_Rr(t_mem code){