## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Verilog Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model for Module 
vlog  "C:/Program Files/Xilinx/verilog/src/glbl.v"
vlog  _translate.v
vlog  i2c_slave_model.v
vsim -t 1ps   -L simprims_ver  -lib work i2c_slave_model glbl
do i2c_slave_model.udo
view wave
add wave *
view structure
view signals
run 1000ns
## End