/******************************************************************************
*monitor.S
*bootstrap monitor service call entry
*Copyright (C) 2004
*T-Engine Application Development Centre (TEADEC)
*License: T-License
*
*Update
*Rev.	Date			Reviser			Description
*1.0	2004/03/23		Jai/Rss/Sin		First release
*1.1	2004/05/05		Jai/Rss/Sin		set SR_I(15) and save registers value
******************************************************************************/
/*""FILE COMMENT""*************************************************************
*       System Name : RENESAS T-Engine, micro T-Engine
*       File Name   : monitor.S
*       Version     : 1.00.00
*       Contents    : bootstrap monitor service call entry
*       Model       : SH7727 T-Engine
*       CPU         : SH7727
*       Compiler    : GNU
*       OS          : T-Kernel, T-Kernel/Standard Extension
*       note        : The Software is being delivered to you "AS IS" 
*                   : and Renesas,whether explicitly or implicitly makes  
*                   : no warranty as to its Use or performance. 
*                   : RENESAS AND ITS SUPPLIER DO NOT AND CANNOT WARRANT 
*                   : THE PERFORMANCE OR RESULTS YOU MAY OBTAIN  BY USING 
*                   : THE SOFTWARE. AS TO ANY MATTER INCLUDING WITHOUT 
*                   : LIMITATION NONINFRINGEMENT OF THIRD PARTY RIGHTS,
*                   : MERCHANTABILITY, INTEGRATION, SATISFACTORY QUALITY, 
*                   : OR FITNESS FOR ANY PARTICULAR PURPOSE.
*
*       Copyright (c) 2004 RENESAS TECHNOLOGY CORP. All Rights Reserved.
*       AND RENESAS SOLUTIONS CORP. All Rights Reserved.
*       history     : 2006.02.03 ver.1.00.00
*""FILE COMMENT END""*********************************************************/

#define _in_asm_source_

	#include <machine.h>
	#include <tk/asm.h>

	.text
	.balign	2
	.globl	Csym(monitor_svc)
	.type	Csym(monitor_svc), @function

Csym(monitor_svc):
	/* During interrupt disable SR.I=15 BL=0 RB=1 */
	mov.l	D_DisableIntSR, r1	// Free exception block
	ldc		r1, sr

	MOVE_ISP_SSP monitor_svc

	mov.l	D_T_MONITOR, r0		// sw bank, SR.I=15 SR_MD
	ldc	r0, sr

	mov.l	r0, @-SP		// save R0_BANK0
	mov.l	r1, @-SP		// save R1_BANK0
	mov.l	r2, @-SP		// save R2_BANK0
	mov.l	r3, @-SP		// save R3_BANK0
	mov.l	r4, @-SP		// save R4_BANK0
	mov.l	r5, @-SP		// save R5_BANK0
	mov.l	r6, @-SP		// save R6_BANK0
	mov.l	r7, @-SP		// save R7_BANK0
	mov.l	r8, @-SP		// save R8
	mov.l	r9, @-SP		// save R9
	mov.l	r10, @-SP		// save R10
	mov.l	r11, @-SP		// save R11
	mov.l	r12, @-SP		// save R12
	mov.l	r13, @-SP		// save R13
	mov.l	r14, @-SP		// save R14
	mov.l	r15, @-SP		// save R15
	sts.l	pr, @-SP

	mov	SP, r14
	mov	r0, r5			// r4 = data r5 = fn code
	mov.l	TM_SVC, r1
	jsr	@r1
	nop

EXIT:
	mov	r14, SP			// Register restore
	lds.l	@SP+, pr
	mov.l	@SP+, r15		// restore R15
	mov.l	@SP+, r14		// restore R14
	mov.l	@SP+, r13		// restore R13
	mov.l	@SP+, r12		// restore R12
	mov.l	@SP+, r11		// restore R11
	mov.l	@SP+, r10		// restore R10
	mov.l	@SP+, r9		// restore R9
	mov.l	@SP+, r8		// restore R8
	mov.l	@SP+, r7		// restore R7_BANK0
	mov.l	@SP+, r6		// restore R6_BANK0
	mov.l	@SP+, r5		// restore R5_BANK0
	mov.l	@SP+, r4		// restore R4_BANK0
	mov.l	@SP+, r3		// restore R3_BANK0
	mov.l	@SP+, r2		// restore R2_BANK0	
	mov.l	@SP+, r1		// restore R1_BANK0
	mov.l	@SP+, r0		// restore R0_BANK0

	mov.l	D_DisableIntSR, r1	// disable Interrupt / Register bank switch RB=1
	ldc	r1, sr
	MOVE_SSP_ISP monitor_svc	// Move from system stack to interrupt stack

	mov.l	D_BlockIntSR, r0	// block Exception
	ldc	r0, sr
	INT_RETURN monitor_svc


	.balign	4
D_DisableIntSR:	.long	SR_MD | SR_I(15) | SR_RB
D_BlockIntSR:	.long	SR_MD | SR_I(15) | SR_RB | SR_BL
D_T_MONITOR:	.long	SR_MD | SR_I(15)

TM_SVC:		.long	Csym(tm_services)