library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder8bit is
   port(cin:in std_logic;
	a,b:in std_logic_vector(7 downto 0);
	s:out std_logic_vector(7 downto 0);
	cout:out std_logic);
end adder8bit;

architecture beh2 of adder8bit is
   component adder4bit
    port(cin:in std_logic;
	a,b:in std_logic_vector(3 downto 0);
	s:out std_logic_vector(3 downto 0);
	cout:out std_logic);
end component;
   signal carry_out:std_logic;
  begin
   u1:adder4bit port map(cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out);
   u2:adder4bit port map(cin=>carry_out,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>cout);
end beh2;