library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div_sheng is
port(
       clk    :    in std_logic;
      tone    :    in std_logic_vector(10 downto 0);
   speaker    :    out std_logic);
end div_sheng;

architecture behave of div_sheng is
signal spk,clks,speak : std_logic;
begin
     process(clk)
     variable counter : integer range 0 to 26;
     begin
        if counter=26 then
           counter:=0;
           clks<='1';
        elsif clk'event and clk='0' then
           counter:=counter+1;
           clks<='0';
        end if;
     end process;

     process(clks)
     variable count : std_logic_vector(10 downto 0);
     begin
        if count="11111111111" then
          count:=tone;
          spk<='1';
        elsif clks'event and clks='0' then
          count:=count+1;
          spk<='0';
        end if;
     end process;

     process(spk)
     begin
          if spk'event and spk='0' then
             speak<=not speak;
             speaker<=speak;
          end if;
     end process;
end behave;