Library IEEE ;
use IEEE.std_logic_1164.all ;


ENTITY reg4_1 is
	PORT(d:in std_logic_vector(3 downto 0);
		clk		: IN   std_logic;
		q:out std_logic_vector(3 downto 0));
END reg4_1;

ARCHITECTURE a OF reg4_1 is
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL clk = '1';
		q <= d;
	END PROCESS;
END a;