?? compilefordebussy
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#!/bin/csh -fif(-e work.lib++) then \rm -rf work.lib++endif# /dq2/qa/Debussy/prod/4.4/Main/bin/vericom \vericom \-v ../verilog/src/mem.v \../verilog/RTL/TopModule.v \../verilog/RTL/ALUB.v \../verilog/RTL/CCU.v \../verilog/FSM/master.v \../verilog/FSM/child1.v \../verilog/FSM/child2.v \../verilog/FSM/child3.vvhdlcom \../vhdl/src/novas.vhd \../vhdl/src/pred_fns.vhd \../vhdl/src/packageCPU.vhd \../vhdl/RTL/arithlogic.vhd \../vhdl/RTL/PCU_record.vhd \../vhdl/src/pram_mixed.vhd \../vhdl/src/system_state.vhd?? 快捷鍵說明
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