Release 7.1i - xst H.38Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.55 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.55 s | Elapsed : 0.00 / 0.00 s --> Reading design: top.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "top.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "top"Output Format                      : NGCTarget Device                      : xc3s400-4-pq208---- Source OptionsTop Module Name                    : topAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : top.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "div_256.v"Module <div_256> compiledCompiling verilog file "DIV16.v"Module <div16> compiledCompiling verilog file "lcd.v"Module <lcd> compiledCompiling verilog file "ps2_keyboard.v"Module <ps2_keyboard_interface> compiledCompiling verilog file "top.vf"Module <top> compiledNo errors in compilationAnalysis of file <"top.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <top>.WARNING:Xst:852 - "top.vf" line 61: Unconnected input port 'rx_read' of instance 'XLXI_4' is tied to GND.WARNING:Xst:852 - "top.vf" line 61: Unconnected input port 'tx_data' of instance 'XLXI_4' is tied to GND.WARNING:Xst:852 - "top.vf" line 61: Unconnected input port 'tx_write' of instance 'XLXI_4' is tied to GND.Module <top> is correct for synthesis.     Set property "resynthesize = true" for unit <top>.Analyzing module <div_256>.Module <div_256> is correct for synthesis. Analyzing module <div16>.Module <div16> is correct for synthesis. Analyzing module <lcd>.	IDLE = <u>00000000000	CLEAR = <u>00000000001	RETURNCURSOR = <u>00000000010	SETMODE = <u>00000000100	SWITCHMODE = <u>00000001000	SHIFT = <u>00000010000	SETFUNCTION = <u>00000100000	SETCGRAM = <u>00001000000	SETDDRAM = <u>00010000000	READFLAG = <u>00100000000	WRITERAM = <u>01000000000	READRAM = <u>10000000000	cur_inc = 1	cur_dec = 0	cur_shift = 1	cur_noshift = 0	open_display = 1	open_cur = 0	blank_cur = 0	shift_display = 1	shift_cur = 0	right_shift = 1	left_shift = 0	datawidth8 = 1	datawidth4 = 0	twoline = 1	oneline = 0	font5x10 = 1	font5x7 = 0Module <lcd> is correct for synthesis. Analyzing module <ps2_keyboard_interface>.	TIMER_60USEC_VALUE_PP = 2950	TIMER_60USEC_BITS_PP = 12	TIMER_5USEC_VALUE_PP = 186	TIMER_5USEC_BITS_PP = 8	TRAP_SHIFT_KEYS_PP = 0	m1_rx_clk_h = 1	m1_rx_clk_l = 0	m1_rx_falling_edge_marker = 13	m1_rx_rising_edge_marker = 14	m1_tx_force_clk_l = 3	m1_tx_first_wait_clk_h = 10	m1_tx_first_wait_clk_l = 11	m1_tx_reset_timer = 12	m1_tx_wait_clk_h = 2	m1_tx_clk_h = 4	m1_tx_clk_l = 5	m1_tx_wait_keyboard_ack = 6	m1_tx_done_recovery = 7	m1_tx_error_no_keyboard_ack = 8	m1_tx_rising_edge_marker = 9	m2_rx_data_ready = 1	m2_rx_data_ready_ack = 0Module <ps2_keyboard_interface> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================INFO:Xst:1304 - Contents of register <lcd_rw> in unit <lcd> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <ps2_keyboard_interface>.    Related source file is "ps2_keyboard.v".WARNING:Xst:1780 - Signal <shift_key_on> is never used or assigned.WARNING:Xst:737 - Found 1-bit latch for signal <rx_data_ready>.    Found 1-bit tristate buffer for signal <ps2_clk>.    Found 1-bit tristate buffer for signal <ps2_data>.    Found 1-bit register for signal <rx_extended>.    Found 1-bit register for signal <rx_released>.    Found 8-bit register for signal <rx_scan_code>.    Found 8-bit register for signal <rx_ascii>.    Found 4-bit up counter for signal <bit_count>.    Found 1-bit 4-to-1 multiplexer for signal <enable_timer_5usec>.    Found 1-bit register for signal <hold_extended>.    Found 1-bit register for signal <hold_released>.    Found 1-bit register for signal <left_shift_key>.    Found 4-bit register for signal <m1_state>.    Found 1-bit register for signal <m2_state>.    Found 1-bit register for signal <ps2_clk_s>.    Found 1-bit register for signal <ps2_data_s>.    Found 11-bit register for signal <q>.    Found 1-bit register for signal <right_shift_key>.    Found 8-bit up counter for signal <timer_5usec_count>.    Found 12-bit up counter for signal <timer_60usec_count>.    Summary:	inferred   3 Counter(s).	inferred  36 D-type flip-flop(s).	inferred   1 Multiplexer(s).	inferred   2 Tristate(s).Unit <ps2_keyboard_interface> synthesized.Synthesizing Unit <lcd>.    Related source file is "lcd.v".INFO:Xst:1799 - State 00000000010 is never reached in FSM <state>.INFO:Xst:1799 - State 00001000000 is never reached in FSM <state>.    Found finite state machine <FSM_0> for signal <state>.    -----------------------------------------------------------------------    | States             | 8                                              |    | Transitions        | 14                                             |    | Inputs             | 6                                              |    | Outputs            | 8                                              |    | Clock              | clk_int (rising_edge)                          |    | Reset              | rst (negative)                                 |    | Reset type         | asynchronous                                   |    | Reset State        | 00000000000                                    |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------WARNING:Xst:737 - Found 8-bit latch for signal <data_in_buf>.    Found 1-bit register for signal <lcd_e>.    Found 1-bit register for signal <lcd_rs>.    Found 8-bit register for signal <data>.    Found 7-bit comparator less for signal <$n0001> created at line 126.    Found 7-bit comparator greater for signal <$n0003> created at line 132.    Found 7-bit comparator less for signal <$n0004> created at line 132.    Found 7-bit adder for signal <$n0031>.    Found 1-bit register for signal <clk_int>.    Found 16-bit up counter for signal <clkcnt>.    Found 1-bit register for signal <clkdiv>.    Found 7-bit register for signal <count>.    Found 1-bit register for signal <flag>.    Summary:	inferred   1 Finite State Machine(s).	inferred   1 Counter(s).	inferred  20 D-type flip-flop(s).	inferred   1 Adder/Subtractor(s).	inferred   3 Comparator(s).Unit <lcd> synthesized.