Synthesizing Unit <div16>.    Related source file is "DIV16.v".    Found 4-bit up counter for signal <count>.    Summary:	inferred   1 Counter(s).Unit <div16> synthesized.Synthesizing Unit <div_256>.    Related source file is "div_256.v".    Found 1-bit register for signal <clk>.    Found 7-bit adder for signal <$old_count_7>.    Found 7-bit register for signal <count>.    Summary:	inferred   8 D-type flip-flop(s).	inferred   1 Adder/Subtractor(s).Unit <div_256> synthesized.Synthesizing Unit <top>.    Related source file is "top.vf".Unit <top> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <state[1:8]> with one-hot encoding.------------------------- State       | Encoding------------------------- 00000000000 | 00000001 00000000001 | 00010000 00000000010 | unreached 00000000100 | 00001000 00000001000 | 10000000 00000010000 | 00000100 00000100000 | 00000010 00001000000 | unreached 00010000000 | 00100000 01000000000 | 01000000-------------------------Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs                             : 1# Adders/Subtractors               : 2 7-bit adder                       : 2# Counters                         : 5 12-bit up counter                 : 1 16-bit up counter                 : 1 4-bit up counter                  : 2 8-bit up counter                  : 1# Registers                        : 47 1-bit register                    : 42 4-bit register                    : 1 7-bit register                    : 2 8-bit register                    : 2# Latches                          : 2 1-bit latch                       : 1 8-bit latch                       : 1# Comparators                      : 3 7-bit comparator greater          : 1 7-bit comparator less             : 2# Multiplexers                     : 1 1-bit 4-to-1 multiplexer          : 1# Tristates                        : 2 1-bit tristate buffer             : 2==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:1710 - FF/Latch  <rx_ascii_7> (without init value) has a constant value of 0 in block <ps2_keyboard_interface>.WARNING:Xst:1291 - FF/Latch <rx_scan_code_6> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <rx_scan_code_0> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <rx_scan_code_5> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <rx_scan_code_4> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <rx_scan_code_3> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <rx_scan_code_7> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <rx_extended> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <hold_extended> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <m2_state> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <rx_scan_code_1> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <rx_scan_code_2> is unconnected in block <XLXI_4>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_data_ready> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_scan_code_6> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_scan_code_0> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_scan_code_5> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_scan_code_4> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_scan_code_3> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_scan_code_7> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_extended> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/hold_extended> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/m2_state> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_scan_code_1> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <XLXI_4/rx_scan_code_2> is unconnected in block <top>.WARNING:Xst:1710 - FF/Latch  <data_in_buf_7> (without init value) has a constant value of 0 in block <lcd>.Optimizing unit <top> ...Optimizing unit <lcd> ...Optimizing unit <div16> ...Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 5.FlipFlop XLXI_4/m1_state_0 has been replicated 1 time(s)FlipFlop XLXI_4/m1_state_1 has been replicated 1 time(s)FlipFlop XLXI_4/m1_state_2 has been replicated 2 time(s)FlipFlop XLXI_4/m1_state_3 has been replicated 1 time(s)FlipFlop XLXI_4/q_1 has been replicated 4 time(s)FlipFlop XLXI_4/q_2 has been replicated 3 time(s)FlipFlop XLXI_4/q_3 has been replicated 2 time(s)FlipFlop XLXI_4/q_4 has been replicated 6 time(s)FlipFlop XLXI_4/q_5 has been replicated 5 time(s)FlipFlop XLXI_4/q_6 has been replicated 6 time(s)FlipFlop XLXI_4/q_7 has been replicated 3 time(s)=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : top.ngrTop Level Output File Name         : topOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 23Macro Statistics :# Registers                        : 47#      1-bit register              : 38#      7-bit register              : 2#      8-bit register              : 7# Multiplexers                     : 1#      1-bit 4-to-1 multiplexer    : 1# Tristates                        : 2#      1-bit tristate buffer       : 2# Adders/Subtractors               : 7#      7-bit adder                 : 2#      8-bit adder                 : 5# Comparators                      : 3#      7-bit comparator greater    : 1#      7-bit comparator less       : 2Cell Usage :# BELS                             : 450#      GND                         : 1#      INV                         : 12#      LUT1                        : 39#      LUT1_L                      : 5#      LUT2                        : 27#      LUT2_D                      : 6#      LUT2_L                      : 5#      LUT3                        : 37#      LUT3_D                      : 2#      LUT3_L                      : 10#      LUT4                        : 108#      LUT4_D                      : 15#      LUT4_L                      : 86#      MUXCY                       : 45#      MUXF5                       : 6#      VCC                         : 1#      XORCY                       : 45# FlipFlops/Latches                : 149#      FD                          : 2#      FDC                         : 18#      FDCE                        : 1#      FDE                         : 17#      FDP                         : 1#      FDR                         : 20#      FDR_1                       : 1#      FDRE                        : 73#      FDRS                        : 7#      FDS                         : 2#      LD_1                        : 7# Clock Buffers                    : 4#      BUFG                        : 3#      BUFGP                       : 1# IO Buffers                       : 22#      IBUF                        : 1#      IOBUF                       : 2#      OBUF                        : 19=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4  Number of Slices:                     188  out of   3584     5%   Number of Slice Flip Flops:           149  out of   7168     2%   Number of 4 input LUTs:               340  out of   7168     4%   Number of bonded IOBs:                 23  out of    141    16%   Number of GCLKs:                        4  out of      8    50%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 12    |XLXI_1/clk:Q                       | BUFG                   | 86    |XLXI_3/clk_int:Q                   | BUFG                   | 25    |XLXI_2/count_3:Q                   | NONE                   | 16    |XLXI_3/tc_clkcnt(XLXI_3/_n003268:O)| NONE(*)(XLXI_3/clkdiv) | 1     |XLXI_3/clkdiv:Q                    | NONE                   | 2     |XLXI_4/rx_released:Q               | BUFG                   | 7     |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Timing Summary:---------------Speed Grade: -4   Minimum period: 7.705ns (Maximum Frequency: 129.786MHz)   Minimum input arrival time before clock: 6.122ns   Maximum output required time after clock: 10.338ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk'  Clock period: 4.274ns (frequency: 233.973MHz)  Total number of paths / destination ports: 45 / 12