`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:17:09 08/24/06
// Design Name:    
// Module Name:    clk2
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module clk2(clk,clock);
input clk;
output clock;
reg clock;
reg[15:0] state;
initial
begin
state<=16'd0;
clock<=0;
end
always@(posedge clk)
begin
state<=state+1;
begin
if (state==16'd499)	 //將50分頻為50K
begin
clock<=~clock;
state<=16'd0;
end
end
end

endmodule