`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:19:16 08/24/06
// Design Name:     謝大釗
// Module Name:    rec2
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module rec2(clk1,rfd,ino,firin,firs);
input clk1,ino,rfd;
output [15:0] firin;
output firs;
reg [15:0] firin="0000000000000000";
reg firs="0";
reg cout="0";
always @(negedge clk1)
begin
if(rfd==1) begin 	 
  
  firs<=1;			
  
		if(ino==1)
      begin
      firin<=16'h7fff;	
      end
      else
      begin
      firin<=16'h8000;	 
      end
end
if(firs==1) begin
firs<=0;
end
end
endmodule