/*-----------------------------------------------------------------------------
*   EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name       : csp_spi.h
* Description     : Definitions, Macros and function declarations for
*                   Serial Peripheral Interface module
* Library Version : 2.00
* Module Version  : 1.XX
*
*       +----- (NEW | MODify | ADD | DELete)                                 
*       |                                                                    
*  No   |   When       Who                What               
*-----+---+----------+------------------+--------------------------------------
* 000  NEW  01/05/99   Patrice VILCHEZ    Creation
* 001  MOD  01/04/01   Olivier MAZUYER    Clean up
* 002  MOD  08/06/01   Frederic SAMSON    Clean Up
* 003  MOD  19/10/01   Christophe GARDIN  Clean Up
* 004  MOD  15/03/02   Christophe GARDIN  Add Macros
*----------------------------------------------------------------------------*/

#ifndef CSP_SPI_H
#define CSP_SPI_H


/******************************************************************************
************************** SPI Structure Definition ***************************
******************************************************************************/

/* Number of SPI Chips Select                                                */
#define NB_SPI_CS 4u

/* Chip Select                                                               */
#define CS0    0u
#define CS1    1u
#define CS2    2u
#define CS3    3u

/******************************************************************************
* SPI Chip Select Structure
******************************************************************************/
typedef struct
{ 
   CSP_REGISTER_T  CSR;                /* Chips Select Registers             */
} CSP_SPI_CS_T, *CSP_SPI_CS_PTR;


/******************************************************************************
* SPI Structure
******************************************************************************/
typedef struct 
{
   CSP_REGISTER_T  PER;                /* PIO Enable Register                */
   CSP_REGISTER_T  PDR;                /* PIO Disable Register               */
   CSP_REGISTER_T  PSR;                /* PIO Status Register                */
   CSP_REGISTER_T  ReservedA;     
   CSP_REGISTER_T  OER;                /* Output Enable Register             */
   CSP_REGISTER_T  ODR;                /* Output Disable Register            */
   CSP_REGISTER_T  OSR;                /* Output Status Register             */
   CSP_REGISTER_T  ReservedB[5];     
   CSP_REGISTER_T  SODR;               /* Set Output Data Register           */
   CSP_REGISTER_T  CODR;               /* Clear Output Data Register         */
   CSP_REGISTER_T  ODSR;               /* Output Data Status Register        */
   CSP_REGISTER_T  PDSR;               /* Pin Data Status Register           */
   CSP_REGISTER_T  MDER;               /* Multi-Driver Enable Register       */
   CSP_REGISTER_T  MDDR;               /* Multi-Driver Disable Register      */
   CSP_REGISTER_T  MDSR;               /* Multi-Driver Status Register       */
   CSP_REGISTER_T  ReservedC;     
   CSP_REGISTER_T  ECR;                /* Enable Clock Register              */
   CSP_REGISTER_T  DCR;                /* Disable Clock Register             */
   CSP_REGISTER_T  PMSR;               /* Power management Status Register   */
   CSP_REGISTER_T  ReservedD;       
   CSP_REGISTER_T  CR;                 /* Control Register                   */
   CSP_REGISTER_T  MR;                 /* Mode Register                      */
   CSP_REGISTER_T  ReservedE[2];
   CSP_REGISTER_T  SR;                 /* Status Register                    */
   CSP_REGISTER_T  IER;                /* Interrupt Enable Register          */
   CSP_REGISTER_T  IDR;                /* Interrupt Disable Register         */
   CSP_REGISTER_T  IMR;                /* Interrupt Mask Register            */
   CSP_REGISTER_T  RDR;                /* Receive Data Register              */
   CSP_REGISTER_T  TDR;                /* Transmit Data Register             */
   CSP_REGISTER_T  ReservedF[2];
   CSP_SPI_CS_T    CS[NB_SPI_CS];      /* Chips Select Registers             */
} CSP_SPI_T, *CSP_SPI_PTR;


/******************************************************************************
************************** SPI Registers Definition ***************************
******************************************************************************/

/******************************************************************************
* PER, PDR, PSR, OER, ODR, OSR,      :
* SODR, CODR, ODSR, PDSR, MDER, MDDR : SPI PIO Registers, Status Register and
* MDSR, SR, IER, IDR, IMR            : Interrupt Registers
******************************************************************************/
#define SPCK         (0x01ul << 16)    /* SCK   as Open Drain                */
#define MISO         (0x01ul << 17)    /* MISO  as Open Drain                */
#define MOSI         (0x01ul << 18)    /* MOSI  as Open Drain                */
#define NPCS0        (0x01ul << 19)    /* NPCS0 as Open Drain                */
#define NPCS1        (0x01ul << 20)    /* NPCS1 as Open Drain                */
#define NPCS2        (0x01ul << 21)    /* NPCS2 as Open Drain                */
#define NPCS3        (0x01ul << 22)    /* NPCS3 as Open Drain                */

/******************************************************************************
* ECR, DCR, PMSR : SPI Power Management Registers
******************************************************************************/ 
#define PIO          (0x01ul << 0)     /* PIO Clock                          */
#define SPI          (0x01ul << 1)     /* SPI Clock                          */

/******************************************************************************
* CR : SPI Control Register
******************************************************************************/
#define SWRST        (0x01ul << 0)     /* SPI Software Reset                 */
#define SPIEN        (0x01ul << 1)     /* SPI Enable Command                 */
#define SPIDIS       (0x01ul << 2)     /* SPI Disable Command                */

/******************************************************************************
* MR : SPI Mode Register
******************************************************************************/
/* MSTR : Master / Slave Mode                                                */
#define MSTR         (0x01ul << 0)     /* MSTR Mask                          */
#define SLAVE        (0x00ul << 0)     /* Slave Mode                         */
#define MASTER       (0x01ul << 0)     /* Master Mode                        */
                           
/* PS : Peripheral Select                                                    */
#define PS           (0x01ul << 1)     /* PS Mask                            */
#define PSFIX        (0x00ul << 1)     /* Fix Peripheral Select              */
#define PSVAR        (0x01ul << 1)     /* Variable Peripheral Select         */
                                       
#define PCSDEC       (0x01ul << 2)     /* Chip Select Decode                 */
#define DIV32        (0x01ul << 3)     /* Clock Selection                    */
#define LLB          (0x01ul << 7)     /* Local Loop Back                    */

/* PCS : Peripheral Chip Select                                              */
#define PCS          (0x0Ful << 16)    /* PCS Mask                           */
/* PCSDEX = 0 : The 4 Chip select directly connected to a peripheral device  */
#define PCS0         (0x0Eul << 16)    /* Peripheral Chip Select 0           */
#define PCS1         (0x01ul << 16)    /* Peripheral Chip Select 1           */
#define PCS2         (0x03ul << 16)    /* Peripheral Chip Select 2           */
#define PCS3         (0x07ul << 16)    /* Peripheral Chip Select 3           */

/* PCSDEX = 1 : The 4 Chip select lines connected to a decoder               */
#define PCS0_OUTPUT  (0x00ul << 16)    /* Output lines = PCS 0               */
#define PCS1_OUTPUT  (0x01ul << 16)    /* Output lines = PCS 1               */