?? series_detection.sim.rpt
字號:
; |series_detection|series:inst|keycod[10]~feeder ; |series_detection|series:inst|keycod[10]~feeder ; combout ;
; |series_detection|series:inst|keycod[3]~feeder ; |series_detection|series:inst|keycod[3]~feeder ; combout ;
; |series_detection|series:inst|keycod[7]~feeder ; |series_detection|series:inst|keycod[7]~feeder ; combout ;
; |series_detection|series:inst|keycod[13]~feeder ; |series_detection|series:inst|keycod[13]~feeder ; combout ;
+-------------------------------------------------+-------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; |series_detection|state:inst1|z ; |series_detection|state:inst1|z ; regout ;
; |series_detection|state:inst1|current_state[3] ; |series_detection|state:inst1|current_state[3] ; regout ;
; |series_detection|state:inst1|current_state[2] ; |series_detection|state:inst1|current_state[2] ; regout ;
; |series_detection|state:inst1|current_state[1] ; |series_detection|state:inst1|current_state[1] ; regout ;
; |series_detection|state:inst1|current_state[5] ; |series_detection|state:inst1|current_state[5] ; regout ;
; |series_detection|state:inst1|current_state[0] ; |series_detection|state:inst1|current_state[0] ; regout ;
; |series_detection|state:inst1|current_state[4] ; |series_detection|state:inst1|current_state[4] ; regout ;
; |series_detection|state:inst1|Mux1~667 ; |series_detection|state:inst1|Mux1~667 ; combout ;
; |series_detection|state:inst1|Mux1~668 ; |series_detection|state:inst1|Mux1~668 ; combout ;
; |series_detection|state:inst1|Mux1~669 ; |series_detection|state:inst1|Mux1~669 ; combout ;
; |series_detection|state:inst1|Mux1~670 ; |series_detection|state:inst1|Mux1~670 ; combout ;
; |series_detection|state:inst1|Mux1~671 ; |series_detection|state:inst1|Mux1~671 ; combout ;
; |series_detection|state:inst1|Mux1~672 ; |series_detection|state:inst1|Mux1~672 ; combout ;
; |series_detection|state:inst1|current_state[7] ; |series_detection|state:inst1|current_state[7] ; regout ;
; |series_detection|state:inst1|current_state[6] ; |series_detection|state:inst1|current_state[6] ; regout ;
; |series_detection|state:inst1|Mux1~673 ; |series_detection|state:inst1|Mux1~673 ; combout ;
; |series_detection|state:inst1|Mux1~674 ; |series_detection|state:inst1|Mux1~674 ; combout ;
; |series_detection|state:inst1|Mux1~675 ; |series_detection|state:inst1|Mux1~675 ; combout ;
; |series_detection|series:inst|clk0 ; |series_detection|series:inst|clk0 ; regout ;
; |series_detection|state:inst1|cnt[4] ; |series_detection|state:inst1|cnt[4] ; regout ;
; |series_detection|state:inst1|cnt[0] ; |series_detection|state:inst1|cnt[0] ; regout ;
; |series_detection|state:inst1|cnt[1] ; |series_detection|state:inst1|cnt[1] ; regout ;
; |series_detection|state:inst1|cnt[2] ; |series_detection|state:inst1|cnt[2] ; regout ;
; |series_detection|state:inst1|cnt[3] ; |series_detection|state:inst1|cnt[3] ; regout ;
; |series_detection|state:inst1|Equal0~34 ; |series_detection|state:inst1|Equal0~34 ; combout ;
; |series_detection|state:inst1|process1~0 ; |series_detection|state:inst1|process1~0 ; combout ;
; |series_detection|state:inst1|next_state[3] ; |series_detection|state:inst1|next_state[3] ; regout ;
; |series_detection|series:inst|clk1 ; |series_detection|series:inst|clk1 ; regout ;
; |series_detection|state:inst1|next_state[2] ; |series_detection|state:inst1|next_state[2] ; regout ;
; |series_detection|state:inst1|next_state[1] ; |series_detection|state:inst1|next_state[1] ; regout ;
; |series_detection|state:inst1|next_state[5] ; |series_detection|state:inst1|next_state[5] ; regout ;
; |series_detection|state:inst1|next_state[0] ; |series_detection|state:inst1|next_state[0] ; regout ;
; |series_detection|state:inst1|next_state[4] ; |series_detection|state:inst1|next_state[4] ; regout ;
; |series_detection|state:inst1|next_state[7] ; |series_detection|state:inst1|next_state[7] ; regout ;
; |series_detection|state:inst1|next_state[6] ; |series_detection|state:inst1|next_state[6] ; regout ;
; |series_detection|series:inst|clkfrq0 ; |series_detection|series:inst|clkfrq0 ; regout ;
; |series_detection|series:inst|cntfrq0[11] ; |series_detection|series:inst|cntfrq0[11] ; regout ;
; |series_detection|series:inst|cntfrq0[9] ; |series_detection|series:inst|cntfrq0[9] ; regout ;
; |series_detection|series:inst|cntfrq0[10] ; |series_detection|series:inst|cntfrq0[10] ; regout ;
; |series_detection|series:inst|Equal0~263 ; |series_detection|series:inst|Equal0~263 ; combout ;
; |series_detection|series:inst|cntfrq0[12] ; |series_detection|series:inst|cntfrq0[12] ; regout ;
; |series_detection|series:inst|cntfrq0[13] ; |series_detection|series:inst|cntfrq0[13] ; regout ;
; |series_detection|series:inst|cntfrq0[14] ; |series_detection|series:inst|cntfrq0[14] ; regout ;
; |series_detection|series:inst|cntfrq0[15] ; |series_detection|series:inst|cntfrq0[15] ; regout ;
; |series_detection|series:inst|Equal0~264 ; |series_detection|series:inst|Equal0~264 ; combout ;
; |series_detection|series:inst|Equal0~265 ; |series_detection|series:inst|Equal0~265 ; combout ;
; |series_detection|series:inst|cntfrq0[16] ; |series_detection|series:inst|cntfrq0[16] ; regout ;
; |series_detection|series:inst|cntfrq0[18] ; |series_detection|series:inst|cntfrq0[18] ; regout ;
; |series_detection|series:inst|cntfrq0[19] ; |series_detection|series:inst|cntfrq0[19] ; regout ;
; |series_detection|series:inst|cntfrq0[17] ; |series_detection|series:inst|cntfrq0[17] ; regout ;
; |series_detection|series:inst|Equal0~266 ; |series_detection|series:inst|Equal0~266 ; combout ;
; |series_detection|series:inst|cntfrq0[24] ; |series_detection|series:inst|cntfrq0[24] ; regout ;
; |series_detection|series:inst|cntfrq0[20] ; |series_detection|series:inst|cntfrq0[20] ; regout ;
; |series_detection|series:inst|cntfrq0[21] ; |series_detection|series:inst|cntfrq0[21] ; regout ;
; |series_detection|series:inst|cntfrq0[22] ; |series_detection|series:inst|cntfrq0[22] ; regout ;
; |series_detection|series:inst|cntfrq0[23] ; |series_detection|series:inst|cntfrq0[23] ; regout ;
; |series_detection|series:inst|Equal0~267 ; |series_detection|series:inst|Equal0~267 ; combout ;
; |series_detection|series:inst|Equal0~268 ; |series_detection|series:inst|Equal0~268 ; combout ;
; |series_detection|series:inst|clk0~64 ; |series_detection|series:inst|clk0~64 ; combout ;
; |series_detection|state:inst1|cnt[1]~18 ; |series_detection|state:inst1|cnt[1]~18 ; combout ;
; |series_detection|state:inst1|cnt[1]~18 ; |series_detection|state:inst1|cnt[1]~22 ; cout ;
; |series_detection|state:inst1|cnt[2]~19 ; |series_detection|state:inst1|cnt[2]~19 ; combout ;
; |series_detection|state:inst1|cnt[2]~19 ; |series_detection|state:inst1|cnt[2]~23 ; cout ;
; |series_detection|state:inst1|cnt[3]~20 ; |series_detection|state:inst1|cnt[3]~20 ; combout ;
; |series_detection|state:inst1|cnt[3]~20 ; |series_detection|state:inst1|cnt[3]~24 ; cout ;
; |series_detection|state:inst1|cnt[4]~21 ; |series_detection|state:inst1|cnt[4]~21 ; combout ;
; |series_detection|series:inst|keycod[16] ; |series_detection|series:inst|keycod[16] ; regout ;
; |series_detection|series:inst|keycod[10] ; |series_detection|series:inst|keycod[10] ; regout ;
; |series_detection|series:inst|keycod[12] ; |series_detection|series:inst|keycod[12] ; regout ;
; |series_detection|series:inst|keycod[8] ; |series_detection|series:inst|keycod[8] ; regout ;
; |series_detection|state:inst1|Mux0~123 ; |series_detection|state:inst1|Mux0~123 ; combout ;
; |series_detection|series:inst|keycod[14] ; |series_detection|series:inst|keycod[14] ; regout ;
; |series_detection|state:inst1|Mux0~124 ; |series_detection|state:inst1|Mux0~124 ; combout ;
; |series_detection|series:inst|keycod[5] ; |series_detection|series:inst|keycod[5] ; regout ;
; |series_detection|series:inst|keycod[3] ; |series_detection|series:inst|keycod[3] ; regout ;
; |series_detection|series:inst|keycod[1] ; |series_detection|series:inst|keycod[1] ; regout ;
; |series_detection|state:inst1|Mux0~125 ; |series_detection|state:inst1|Mux0~125 ; combout ;
; |series_detection|series:inst|keycod[7] ; |series_detection|series:inst|keycod[7] ; regout ;
; |series_detection|state:inst1|Mux0~126 ; |series_detection|state:inst1|Mux0~126 ; combout ;
; |series_detection|series:inst|keycod[4] ; |series_detection|series:inst|keycod[4] ; regout ;
; |series_detection|series:inst|keycod[2] ; |series_detection|series:inst|keycod[2] ; regout ;
; |series_detection|series:inst|keycod[0] ; |series_detection|series:inst|keycod[0] ; regout ;
; |series_detection|state:inst1|Mux0~127 ; |series_detection|state:inst1|Mux0~127 ; combout ;
; |series_detection|series:inst|keycod[6] ; |series_detection|series:inst|keycod[6] ; regout ;
; |series_detection|state:inst1|Mux0~128 ; |series_detection|state:inst1|Mux0~128 ; combout ;
; |series_detection|state:inst1|Mux0~129 ; |series_detection|state:inst1|Mux0~129 ; combout ;
; |series_detection|series:inst|keycod[11] ; |series_detection|series:inst|keycod[11] ; regout ;
; |series_detection|series:inst|keycod[13] ; |series_detection|series:inst|keycod[13] ; regout ;
; |series_detection|series:inst|keycod[9] ; |series_detection|series:inst|keycod[9] ; regout ;
; |series_detection|state:inst1|Mux0~130 ; |series_detection|state:inst1|Mux0~130 ; combout ;
; |series_detection|series:inst|keycod[15] ; |series_detection|series:inst|keycod[15] ; regout ;
; |series_detection|state:inst1|Mux0~131 ; |series_detection|state:inst1|Mux0~131 ; combout ;
; |series_detection|state:inst1|Mux0~132 ; |series_detection|state:inst1|Mux0~132 ; combout ;
; |series_detection|state:inst1|Mux0~133 ; |series_detection|state:inst1|Mux0~133 ; combout ;
; |series_detection|state:inst1|Mux8~308 ; |series_detection|state:inst1|Mux8~308 ; combout ;
; |series_detection|state:inst1|Mux7~298 ; |series_detection|state:inst1|Mux7~298 ; combout ;
; |series_detection|state:inst1|Mux6~297 ; |series_detection|state:inst1|Mux6~297 ; combout ;
; |series_detection|series:inst|clkfrq1 ; |series_detection|series:inst|clkfrq1 ; regout ;
; |series_detection|series:inst|cntfrq1[9] ; |series_detection|series:inst|cntfrq1[9] ; regout ;
; |series_detection|series:inst|cntfrq1[10] ; |series_detection|series:inst|cntfrq1[10] ; regout ;
; |series_detection|series:inst|cntfrq1[11] ; |series_detection|series:inst|cntfrq1[11] ; regout ;
; |series_detection|series:inst|cntfrq1[13] ; |series_detection|series:inst|cntfrq1[13] ; regout ;
; |series_detection|series:inst|cntfrq1[14] ; |series_detection|series:inst|cntfrq1[14] ; regout ;
; |series_detection|series:inst|cntfrq1[12] ; |series_detection|series:inst|cntfrq1[12] ; regout ;
; |series_detection|series:inst|Equal1~144 ; |series_detection|series:inst|Equal1~144 ; combout ;
; |series_detection|series:inst|Equal1~145 ; |series_detection|series:inst|Equal1~145 ; combout ;
; |series_detection|series:inst|clk1~167 ; |series_detection|series:inst|clk1~167 ; combout ;
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