?? ct24.rpt
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Project Information e:\cpld工程\ct24.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 09/18/2008 19:52:16
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
ct24 EPM7032SLC44-5 2 5 0 5 0 15 %
User Pins: 2 5 0
Project Information e:\cpld工程\ct24.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
INFO: Signal 'clr' chosen for auto global Clear
Project Information e:\cpld工程\ct24.rpt
** FILE HIERARCHY **
|c24:1|
|c24:1|74161:1|
|c24:1|74161:1|p74161:sub|
|c24:1|74161:2|
|c24:1|74161:2|p74161:sub|
Device-Specific Information: e:\cpld工程\ct24.rpt
ct24
***** Logic for device 'ct24' compiled without errors.
Device: EPM7032SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
R R R
E E E
S S S
E E E
R R R
V V V V G c G c G
E E E C N l N l N q q
D D D C D r D k D 2 1
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | q3
RESERVED | 8 38 | #TDO
RESERVED | 9 37 | q4
GND | 10 36 | q0
RESERVED | 11 35 | VCC
RESERVED | 12 EPM7032SLC44-5 34 | RESERVED
#TMS | 13 33 | RESERVED
RESERVED | 14 32 | #TCK
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\cpld工程\ct24.rpt
ct24
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 2/16( 12%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 5/16( 31%) 7/16( 43%) 0/16( 0%) 5/36( 13%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 9/32 ( 28%)
Total logic cells used: 5/32 ( 15%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 5/32 ( 15%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 5.20
Total fan-in: 26
Total input pins required: 2
Total fast input logic cells required: 0
Total output pins required: 5
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 5
Total flipflops required: 5
Total product terms required: 7
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\cpld工程\ct24.rpt
ct24
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clk
1 - - INPUT G 0 0 0 0 0 0 0 clr
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\cpld工程\ct24.rpt
ct24
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
36 22 B FF + t 0 0 0 0 0 4 0 q0 (|c24:1|74161:1|p74161:sub|:9)
40 18 B FF + t 0 0 0 0 1 3 0 q1 (|c24:1|74161:1|p74161:sub|:8)
41 17 B FF + t 0 0 0 0 2 2 0 q2 (|c24:1|74161:1|p74161:sub|:7)
39 19 B FF + t 0 0 0 0 5 2 0 q3 (|c24:1|74161:1|p74161:sub|:6)
37 21 B FF + t 0 0 0 0 5 2 0 q4 (|c24:1|74161:2|p74161:sub|:9)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\cpld工程\ct24.rpt
ct24
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------- LC22 q0
| +------- LC18 q1
| | +----- LC17 q2
| | | +--- LC19 q3
| | | | +- LC21 q4
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'B'
LC | | | | | | A B | Logic cells that feed LAB 'B':
LC22 -> * * * * * | - * | <-- q0
LC18 -> - * * * * | - * | <-- q1
LC17 -> - - * * * | - * | <-- q2
LC19 -> - - - * * | - * | <-- q3
LC21 -> - - - * * | - * | <-- q4
Pin
43 -> - - - - - | - - | <-- clk
1 -> - - - - - | - - | <-- clr
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpld工程\ct24.rpt
ct24
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is 'q0' = '|c24:1|74161:1|p74161:sub|QA'
-- Equation name is 'q0', type is output
q0 = TFFE( VCC, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
-- Node name is 'q1' = '|c24:1|74161:1|p74161:sub|QB'
-- Equation name is 'q1', type is output
q1 = TFFE( q0, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
-- Node name is 'q2' = '|c24:1|74161:1|p74161:sub|QC'
-- Equation name is 'q2', type is output
q2 = TFFE( _EQ001, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ001 = q0 & q1;
-- Node name is 'q3' = '|c24:1|74161:1|p74161:sub|QD'
-- Equation name is 'q3', type is output
q3 = TFFE( _EQ002, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ002 = q0 & q1 & q2 & !q3 & !q4
# q0 & q1 & q2 & q3;
-- Node name is 'q4' = '|c24:1|74161:2|p74161:sub|QA'
-- Equation name is 'q4', type is output
q4 = TFFE( _EQ003, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ003 = q0 & q1 & q2 & q3 & !q4
# q0 & q1 & q2 & q4;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\cpld工程\ct24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,011K
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