<?xml version="1.0" encoding="UTF-8"?>
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<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">N697</arg> has no load.
</msg>

<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">1</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">N698</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>

<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>

<msg type="info" file="MapLib" num="535" delta="unknown" >The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFGP symbol &quot;clk_BUFGP&quot; (output signal=clk_BUFGP),
BUFGP symbol &quot;reset_BUFGP&quot; (output signal=reset_BUFGP)</arg>
</msg>

<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>

<msg type="warning" file="LIT" num="175" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;physical_group_reset_BUFGP/reset_BUFGP/BUFG&quot; (output signal=reset_BUFGP)</arg> has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
<arg fmt="%s" index="2">Pin CLR of uart_rx_unit/b_reg_0
Pin CLR of uart_rx_unit/b_reg_1
Pin CLR of uart_rx_unit/b_reg_2
Pin CLR of uart_rx_unit/b_reg_3
Pin CLR of uart_rx_unit/b_reg_4</arg>
</msg>

</messages>