Release 9.2i Map J.36Xilinx Mapping Report File for Design 'vgavga'Design Information------------------Command Line   : E:\Program Files\xp\Xilinx92i\bin\nt\map.exe -ise E:/Program
Files/xp/Xilinx92i/mydesign/vgavga/vgavga.ise -intstyle ise -p xc3s200-ft256-4
-cm area -pr b -k 4 -c 100 -o vgavga_map.ncd vgavga.ngd vgavga.pcf Target Device  : xc3s200Target Package : ft256Target Speed   : -4Mapper Version : spartan3 -- $Revision: 1.36 $Mapped Date    : Sun Jun 01 01:44:13 2008Design Summary--------------Number of errors:      0Number of warnings:    0Logic Utilization:  Number of Slice Flip Flops:          22 out of   3,840    1%  Number of 4 input LUTs:              19 out of   3,840    1%Logic Distribution:  Number of occupied Slices:                           20 out of   1,920    1%    Number of Slices containing only related logic:      20 out of      20  100%    Number of Slices containing unrelated logic:          0 out of      20    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs:             36 out of   3,840    1%  Number used as logic:                 19  Number used as a route-thru:          17  Number of bonded IOBs:                8 out of     173    4%    IOB Flip Flops:                     3  Number of GCLKs:                     2 out of       8   25%  Number of DCMs:                      1 out of       4   25%Total equivalent gate count for design:  7,422Additional JTAG gate count for IOBs:  384Peak Memory Usage:  135 MBTotal REAL time to MAP completion:  1 secs Total CPU time to MAP completion:   1 secs NOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Control Set InformationSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:863 - The following Virtex BUFG(s) is/are being retargeted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:   BUFG symbol "instance_name/CLK0_BUFG_INST" (output
   signal=instance_name/CLK0_OUT),   BUFG symbol "instance_name/CLKFX_BUFG_INST" (output signal=clk)INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   instance_name/DCM_INST/instance_name/DCM_INST, consult the device Interactive
   Data Sheet.Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| clock                              | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || key<0>                             | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || key<1>                             | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || vga_B                              | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || vga_G                              | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || vga_R                              | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || vga_h_sync                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || vga_v_sync                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------Area Group Information----------------------  No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Control Set Information------------------------------------No control set information for this architecture.