<?xml version="1.0" encoding="UTF-8"?>
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<messages>
<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>

<msg type="info" file="MapLib" num="863" delta="unknown" >The following Virtex BUFG(s) is/are being retargeted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFG symbol &quot;instance_name/CLK0_BUFG_INST&quot; (output signal=instance_name/CLK0_OUT),
BUFG symbol &quot;instance_name/CLKFX_BUFG_INST&quot; (output signal=clk)</arg>
</msg>

<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>

<msg type="info" file="PhysDesignRules" num="772" delta="unknown" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">instance_name/DCM_INST/instance_name/DCM_INST</arg>, consult the device Interactive Data Sheet.
</msg>

</messages>