?? bin27seg_vhd_vec_tst.vhd
字號:
--另外,行為級的描述常常被用來產生仿真時的測試向量(testbench)文件。
--例如對于本節開始處提到的LED譯碼電路,可以編寫如下測試向量文件。
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bin27seg_vhd_vec_tst IS
END bin27seg_vhd_vec_tst;
ARCHITECTURE bin27seg_arch OF bin27seg_vhd_vec_tst IS
-- constants
-- signals
SIGNAL t_sig_data_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL t_sig_data_out : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL t_sig_EN : STD_LOGIC;
COMPONENT bin27seg
PORT (
data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
EN : IN STD_LOGIC
);
END COMPONENT;
BEGIN
tb : bin27seg
PORT MAP (
-- list connections between master ports and signals
data_in => t_sig_data_in,
data_out => t_sig_data_out,
EN => t_sig_EN
);
-- data_in[3]
t_prcs_data_in_3: PROCESS
BEGIN
t_sig_data_in(3) <= '0';
WAIT FOR 300000 ps;
t_sig_data_in(3) <= '1';
WAIT FOR 295000 ps;
t_sig_data_in(3) <= '0';
WAIT FOR 145000 ps;
t_sig_data_in(3) <= '1';
WAIT;
END PROCESS t_prcs_data_in_3;
-- data_in[2]
t_prcs_data_in_2: PROCESS
BEGIN
t_sig_data_in(2) <= '0';
WAIT FOR 595000 ps;
t_sig_data_in(2) <= '1';
WAIT FOR 280000 ps;
t_sig_data_in(2) <= '0';
WAIT;
END PROCESS t_prcs_data_in_2;
-- data_in[1]
t_prcs_data_in_1: PROCESS
BEGIN
t_sig_data_in(1) <= '0';
WAIT FOR 455000 ps;
t_sig_data_in(1) <= '1';
WAIT FOR 140000 ps;
t_sig_data_in(1) <= '0';
WAIT FOR 145000 ps;
t_sig_data_in(1) <= '1';
WAIT FOR 135000 ps;
t_sig_data_in(1) <= '0';
WAIT;
END PROCESS t_prcs_data_in_1;
-- data_in[0]
t_prcs_data_in_0: PROCESS
BEGIN
t_sig_data_in(0) <= '0';
WAIT FOR 165000 ps;
t_sig_data_in(0) <= '1';
WAIT FOR 135000 ps;
t_sig_data_in(0) <= '0';
WAIT FOR 295000 ps;
t_sig_data_in(0) <= '1';
WAIT;
END PROCESS t_prcs_data_in_0;
-- EN
t_prcs_EN: PROCESS
BEGIN
t_sig_EN <= '0';
WAIT FOR 75000 ps;
t_sig_EN <= '1';
WAIT;
END PROCESS t_prcs_EN;
END bin27seg_arch;
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