{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 18 13:24:00 2007 " "Info: Processing started: Sun Feb 18 13:24:00 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off tst_mult -c tst_mult --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tst_mult -c tst_mult --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] q_out\[1\] 13.112 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"q_out\[1\]\" is 13.112 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns a\[0\] 1 PIN PIN_U25 16 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U25; Fanout = 16; PIN Node = 'a\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "tst_mult.vhd" "" { Text "F:/復件 tijiao/程序及軟件/cht04/s04p11tst_mult/tst_mult.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.142 ns) + CELL(2.831 ns) 8.207 ns lpm_mult:u1\|mult_p2o:auto_generated\|mac_mult2~DATAOUT15 2 COMB DSPMULT_X10_Y7_N0 16 " "Info: 2: + IC(4.142 ns) + CELL(2.831 ns) = 8.207 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; COMB Node = 'lpm_mult:u1\|mult_p2o:auto_generated\|mac_mult2~DATAOUT15'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.973 ns" { a[0] lpm_mult:u1|mult_p2o:auto_generated|mac_mult2~DATAOUT15 } "NODE_NAME" } } { "db/mult_p2o.tdf" "" { Text "F:/復件 tijiao/程序及軟件/cht04/s04p11tst_mult/db/mult_p2o.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.878 ns) 9.085 ns lpm_mult:u1\|mult_p2o:auto_generated\|result\[1\] 3 COMB DSPOUT_X11_Y1_N0 1 " "Info: 3: + IC(0.000 ns) + CELL(0.878 ns) = 9.085 ns; Loc. = DSPOUT_X11_Y1_N0; Fanout = 1; COMB Node = 'lpm_mult:u1\|mult_p2o:auto_generated\|result\[1\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { lpm_mult:u1|mult_p2o:auto_generated|mac_mult2~DATAOUT15 lpm_mult:u1|mult_p2o:auto_generated|result[1] } "NODE_NAME" } } { "db/mult_p2o.tdf" "" { Text "F:/復件 tijiao/程序及軟件/cht04/s04p11tst_mult/db/mult_p2o.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.623 ns) + CELL(2.404 ns) 13.112 ns q_out\[1\] 4 PIN PIN_AF19 0 " "Info: 4: + IC(1.623 ns) + CELL(2.404 ns) = 13.112 ns; Loc. = PIN_AF19; Fanout = 0; PIN Node = 'q_out\[1\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.027 ns" { lpm_mult:u1|mult_p2o:auto_generated|result[1] q_out[1] } "NODE_NAME" } } { "tst_mult.vhd" "" { Text "F:/復件 tijiao/程序及軟件/cht04/s04p11tst_mult/tst_mult.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.347 ns ( 56.03 % ) " "Info: Total cell delay = 7.347 ns ( 56.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.765 ns ( 43.97 % ) " "Info: Total interconnect delay = 5.765 ns ( 43.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "13.112 ns" { a[0] lpm_mult:u1|mult_p2o:auto_generated|mac_mult2~DATAOUT15 lpm_mult:u1|mult_p2o:auto_generated|result[1] q_out[1] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "13.112 ns" { a[0] a[0]~out0 lpm_mult:u1|mult_p2o:auto_generated|mac_mult2~DATAOUT15 lpm_mult:u1|mult_p2o:auto_generated|result[1] q_out[1] } { 0.000ns 0.000ns 4.142ns 0.000ns 1.623ns } { 0.000ns 1.234ns 2.831ns 0.878ns 2.404ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 18 13:24:01 2007 " "Info: Processing ended: Sun Feb 18 13:24:01 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}