<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30</td><td align="CENTER"><a name="US_COMM_TX"></a><b>US_COMM_TX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_COMM_TX">AT91C_US_COMM_TX</a></font></td><td><b>COMM_TX Interrupt</b><br>0 = COMM_TX is at 0.<br>1 = COMM_TX is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31</td><td align="CENTER"><a name="US_COMM_RX"></a><b>US_COMM_RX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_COMM_RX">AT91C_US_COMM_RX</a></font></td><td><b>COMM_RX Interrupt</b><br>0 = COMM_RX is at 0.<br>1 = COMM_RX is at 1.</td></tr>
</null></table>
<a name="DBGU_IMR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> DBGU_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91RM9200_h.html#AT91C_DBGU_IMR">AT91C_DBGU_IMR</a></i> 0xFFFFF210</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30</td><td align="CENTER"><a name="US_COMM_TX"></a><b>US_COMM_TX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_COMM_TX">AT91C_US_COMM_TX</a></font></td><td><b>COMM_TX Interrupt</b><br>0 = COMM_TX is at 0.<br>1 = COMM_TX is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31</td><td align="CENTER"><a name="US_COMM_RX"></a><b>US_COMM_RX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_COMM_RX">AT91C_US_COMM_RX</a></font></td><td><b>COMM_RX Interrupt</b><br>0 = COMM_RX is at 0.<br>1 = COMM_RX is at 1.</td></tr>
</null></table>
<a name="DBGU_CSR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> DBGU_CSR  <i>Channel Status Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91RM9200_h.html#AT91C_DBGU_CSR">AT91C_DBGU_CSR</a></i> 0xFFFFF214</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30</td><td align="CENTER"><a name="US_COMM_TX"></a><b>US_COMM_TX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_COMM_TX">AT91C_US_COMM_TX</a></font></td><td><b>COMM_TX Interrupt</b><br>0 = COMM_TX is at 0.<br>1 = COMM_TX is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31</td><td align="CENTER"><a name="US_COMM_RX"></a><b>US_COMM_RX</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_COMM_RX">AT91C_US_COMM_RX</a></font></td><td><b>COMM_RX Interrupt</b><br>0 = COMM_RX is at 0.<br>1 = COMM_RX is at 1.</td></tr>
</null></table>
<a name="DBGU_RHR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> DBGU_RHR  <i>Receiver Holding Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91RM9200_h.html#AT91C_DBGU_RHR">AT91C_DBGU_RHR</a></i> 0xFFFFF218</font></null></ul><br>Last character received if RXRDY is set. When number of data bits is less than 8 bits, the bits are right-aligned. All non-sig-nificant bits read zero.<a name="DBGU_THR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> DBGU_THR  <i>Transmitter Holding Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91RM9200_h.html#AT91C_DBGU_THR">AT91C_DBGU_THR</a></i> 0xFFFFF21C</font></null></ul><br>Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned.<a name="DBGU_BRGR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> DBGU_BRGR  <i>Baud Rate Generator Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91RM9200_h.html#AT91C_DBGU_BRGR">AT91C_DBGU_BRGR</a></i> 0xFFFFF220</font></null></ul><br>Clock Divisor:<br>0 Disables Clock<br>1 Clock Divisor Bypass<br>2 to 65535 Baud Rate = Selected Clock / (CDx16)<a name="DBGU_C1R"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> DBGU_C1R  <i>Chip ID1 Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91RM9200_h.html#AT91C_DBGU_C1R">AT91C_DBGU_C1R</a></i> 0xFFFFF240</font></null></ul><br>Hard-coded value. Must be specified before debug unit synthesis.<a name="DBGU_C2R"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> DBGU_C2R  <i>Chip ID2 Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91RM9200_h.html#AT91C_DBGU_C2R">AT91C_DBGU_C2R</a></i> 0xFFFFF244</font></null></ul><br>Hard-coded value. Must be specified before debug unit synthesis.<a name="DBGU_FNTR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> DBGU_FNTR  <i>Force NTRST Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91RM9200_h.html#AT91C_DBGU_FNTR">AT91C_DBGU_FNTR</a></i> 0xFFFFF248</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_FORCE_NTRST"></a><b>US_FORCE_NTRST</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_US_FORCE_NTRST">AT91C_US_FORCE_NTRST</a></font></td><td><b>Force NTRST in JTAG</b><br>0 = NTRST is not forced.<br>1 = NTRST is forced.</td></tr>
</null></table>
<a name="DBGU_PDC"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91RM9200_h.html#AT91S_PDC">AT91S_PDC</a></i> DBGU_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="#AT91C_DBGU_DBGU">AT91C_DBGU_DBGU</a></i> 0xFFFFF300</font></null></ul></null><hr></html>