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<h1>SDRAM Controller Interface Peripheral</h1>
<null><a name="SDRC"></a><b>SDRC</b> <i><font size="-1">(<a href="AT91RM9200_h.html#AT91S_SDRC">AT91S_SDRC</a>)</font></i><b> 0xFFFFFF90 </b><i><font size="-1">(<a href="AT91RM9200_h.html#AT91C_BASE_SDRC">AT91C_BASE_SDRC</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1"><b>Signal</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Symbol</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>PIO controller</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b>
</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>D20</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC20_D20 ">AT91C_PC20_D20 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 20</font></td><td><font size="-1">Data Bus [20]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D21</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC21_D21 ">AT91C_PC21_D21 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 21</font></td><td><font size="-1">Data Bus [21]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D30</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC30_D30 ">AT91C_PC30_D30 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 30</font></td><td><font size="-1">Data Bus [30]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D22</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC22_D22 ">AT91C_PC22_D22 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 22</font></td><td><font size="-1">Data Bus [22]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D31</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC31_D31 ">AT91C_PC31_D31 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 31</font></td><td><font size="-1">Data Bus [31]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D23</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC23_D23 ">AT91C_PC23_D23 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 23</font></td><td><font size="-1">Data Bus [23]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D16</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC16_D16 ">AT91C_PC16_D16 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 16</font></td><td><font size="-1">Data Bus [16]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D24</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC24_D24 ">AT91C_PC24_D24 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 24</font></td><td><font size="-1">Data Bus [24]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D17</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC17_D17 ">AT91C_PC17_D17 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 17</font></td><td><font size="-1">Data Bus [17]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D25</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC25_D25 ">AT91C_PC25_D25 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 25</font></td><td><font size="-1">Data Bus [25]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D18</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC18_D18 ">AT91C_PC18_D18 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 18</font></td><td><font size="-1">Data Bus [18]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D26</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC26_D26 ">AT91C_PC26_D26 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 26</font></td><td><font size="-1">Data Bus [26]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D19</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC19_D19 ">AT91C_PC19_D19 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 19</font></td><td><font size="-1">Data Bus [19]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D27</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC27_D27 ">AT91C_PC27_D27 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 27</font></td><td><font size="-1">Data Bus [27]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D28</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC28_D28 ">AT91C_PC28_D28 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 28</font></td><td><font size="-1">Data Bus [28]</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>D29</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PC29_D29 ">AT91C_PC29_D29 </a>)</font></i></font></td><td><font size="-1"><a href="#PIOC">PIOC</a> Periph: A Bit: 29</font></td><td><font size="-1">Data Bus [29]</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_SDRC_CfgPIO">AT91F_SDRC_CfgPIO</a></b></font></td><td><font size="-1">Configure PIO controllers to drive SDRC signals</font></td></tr>
</null></table><br><br></null><a name="SDRC"></a><h2>SDRC Software API <i><font size="-1">(<a href="AT91RM9200_h.html#AT91S_SDRC">AT91S_SDRC</a>)</font></i></h2>
<a name="SDRC"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91RM9200_SDRC.html#SDRC_MR">SDRC_MR</a></font></td><td><font size="-1">SDRAM Controller Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91RM9200_SDRC.html#SDRC_TR">SDRC_TR</a></font></td><td><font size="-1">SDRAM Controller Refresh Timer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x8</b></font></td><td><font size="-1"><a href="AT91RM9200_SDRC.html#SDRC_CR">SDRC_CR</a></font></td><td><font size="-1">SDRAM Controller Configuration Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91RM9200_SDRC.html#SDRC_SRR">SDRC_SRR</a></font></td><td><font size="-1">SDRAM Controller Self Refresh Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1"><a href="AT91RM9200_SDRC.html#SDRC_LPR">SDRC_LPR</a></font></td><td><font size="-1">SDRAM Controller Low Power Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x14</b></font></td><td><font size="-1"><a href="AT91RM9200_SDRC.html#SDRC_IER">SDRC_IER</a></font></td><td><font size="-1">SDRAM Controller Interrupt Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x18</b></font></td><td><font size="-1"><a href="AT91RM9200_SDRC.html#SDRC_IDR">SDRC_IDR</a></font></td><td><font size="-1">SDRAM Controller Interrupt Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x1C</b></font></td><td><font size="-1"><a href="AT91RM9200_SDRC.html#SDRC_IMR">SDRC_IMR</a></font></td><td><font size="-1">SDRAM Controller Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x20</b></font></td><td><font size="-1"><a href="AT91RM9200_SDRC.html#SDRC_ISR">SDRC_ISR</a></font></td><td><font size="-1">SDRAM Controller Interrupt Mask Register</font></td></tr>
</null></table><br></null><h2>SDRC Register Description</h2>
<null><a name="SDRC_MR"></a><h4><a href="#SDRC">SDRC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> SDRC_MR <i>SDRAM Controller Mode Register</i></h4><ul><null><font size="-2"><li><b>SDRC</b> <i><a href="AT91RM9200_h.html#AT91C_SDRC_MR">AT91C_SDRC_MR</a></i> 0xFFFFFF90</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">3..0</td><td align="CENTER"><a name="SDRC_MODE"></a><b>SDRC_MODE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_SDRC_MODE">AT91C_SDRC_MODE</a></font></td><td><b>Mode</b><br>0: Normal Mode.<br>1: Issue a NOP Command at every access.<br>2: Issue a All Banks Precharge Command at every access.<br><br> 3: Issue a Load Mode Register at every access.<br>4: Issue a Refresh<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SDRC_MODE_NORMAL_CMD"></a><b>SDRC_MODE_NORMAL_CMD</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_SDRC_MODE_NORMAL_CMD">AT91C_SDRC_MODE_NORMAL_CMD</a></font></td><td><br>Normal Mode</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SDRC_MODE_NOP_CMD"></a><b>SDRC_MODE_NOP_CMD</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_SDRC_MODE_NOP_CMD">AT91C_SDRC_MODE_NOP_CMD</a></font></td><td><br>NOP Command</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SDRC_MODE_PRCGALL_CMD"></a><b>SDRC_MODE_PRCGALL_CMD</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_SDRC_MODE_PRCGALL_CMD">AT91C_SDRC_MODE_PRCGALL_CMD</a></font></td><td><br>All Banks Precharge Command</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SDRC_MODE_LMR_CMD"></a><b>SDRC_MODE_LMR_CMD</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_SDRC_MODE_LMR_CMD">AT91C_SDRC_MODE_LMR_CMD</a></font></td><td><br>Load Mode Register Command</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SDRC_MODE_RFSH_CMD"></a><b>SDRC_MODE_RFSH_CMD</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_SDRC_MODE_RFSH_CMD">AT91C_SDRC_MODE_RFSH_CMD</a></font></td><td><br>Refresh Command</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SDRC_DBW"></a><b>SDRC_DBW</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_SDRC_DBW">AT91C_SDRC_DBW</a></font></td><td><b>Data Bus Width</b><br>0: 32 bits.<br>1: 16bits.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SDRC_DBW_32_BITS"></a><b>SDRC_DBW_32_BITS</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_SDRC_DBW_32_BITS">AT91C_SDRC_DBW_32_BITS</a></font></td><td><br>32 Bits datas bus</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SDRC_DBW_16_BITS"></a><b>SDRC_DBW_16_BITS</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_SDRC_DBW_16_BITS">AT91C_SDRC_DBW_16_BITS</a></font></td><td><br>16 Bits datas bus</td></tr>
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