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<h1>System Peripherals Peripheral</h1>
<null><a name="SYS"></a><b>SYS</b> <i><font size="-1">(<a href="AT91RM9200_h.html#AT91S_SYS">AT91S_SYS</a>)</font></i><b> 0xFFFFF000 </b><i><font size="-1">(<a href="AT91RM9200_h.html#AT91C_BASE_SYS">AT91C_BASE_SYS</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1">Periph ID <a href="#AIC">AIC</a></font></th><th bgcolor="#FFFFCC"><font size="-1">Symbol</font></th><th bgcolor="#FFFFCC"><font size="-1">Description</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>1</b> </font></td><td><font size="-1"><i><font size="-1">(<a href="AT91RM9200_h.html#AT91C_ID_SYS">AT91C_ID_SYS</a>)</font></i></font></td><td><font size="-1">System Peripheral</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_SYS_CfgPMC">AT91F_SYS_CfgPMC</a></b></font></td><td><font size="-1">Enable Peripheral clock in PMC for SYS</font></td></tr>
</null></table><br><br></null><a name="SYS"></a><h2>SYS Software API <i><font size="-1">(<a href="AT91RM9200_h.html#AT91S_SYS">AT91S_SYS</a>)</font></i></h2>
<a name="SYS"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1">AIC_SMR[32] (<a href="#AIC_SMR">AIC_SMR</a>)</font></td><td><font size="-1">Source Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x80</b></font></td><td><font size="-1">AIC_SVR[32] (<a href="#AIC_SVR">AIC_SVR</a>)</font></td><td><font size="-1">Source Vector Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x100</b></font></td><td><font size="-1"><a href="#AIC_IVR">AIC_IVR</a></font></td><td><font size="-1">IRQ Vector Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x104</b></font></td><td><font size="-1"><a href="#AIC_FVR">AIC_FVR</a></font></td><td><font size="-1">FIQ Vector Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x108</b></font></td><td><font size="-1"><a href="#AIC_ISR">AIC_ISR</a></font></td><td><font size="-1">Interrupt Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10C</b></font></td><td><font size="-1"><a href="#AIC_IPR">AIC_IPR</a></font></td><td><font size="-1">Interrupt Pending Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x110</b></font></td><td><font size="-1"><a href="#AIC_IMR">AIC_IMR</a></font></td><td><font size="-1">Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x114</b></font></td><td><font size="-1"><a href="#AIC_CISR">AIC_CISR</a></font></td><td><font size="-1">Core Interrupt Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x120</b></font></td><td><font size="-1"><a href="#AIC_IECR">AIC_IECR</a></font></td><td><font size="-1">Interrupt Enable Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x124</b></font></td><td><font size="-1"><a href="#AIC_IDCR">AIC_IDCR</a></font></td><td><font size="-1">Interrupt Disable Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x128</b></font></td><td><font size="-1"><a href="#AIC_ICCR">AIC_ICCR</a></font></td><td><font size="-1">Interrupt Clear Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x12C</b></font></td><td><font size="-1"><a href="#AIC_ISCR">AIC_ISCR</a></font></td><td><font size="-1">Interrupt Set Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x130</b></font></td><td><font size="-1"><a href="#AIC_EOICR">AIC_EOICR</a></font></td><td><font size="-1">End of Interrupt Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x134</b></font></td><td><font size="-1"><a href="#AIC_SPU">AIC_SPU</a></font></td><td><font size="-1">Spurious Vector Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x138</b></font></td><td><font size="-1"><a href="#AIC_DCR">AIC_DCR</a></font></td><td><font size="-1">Debug Control Register (Protect)</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x140</b></font></td><td><font size="-1"><a href="#AIC_FFER">AIC_FFER</a></font></td><td><font size="-1">Fast Forcing Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x144</b></font></td><td><font size="-1"><a href="#AIC_FFDR">AIC_FFDR</a></font></td><td><font size="-1">Fast Forcing Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x148</b></font></td><td><font size="-1"><a href="#AIC_FFSR">AIC_FFSR</a></font></td><td><font size="-1">Fast Forcing Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x200</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_CR">DBGU_CR</a></font></td><td><font size="-1">Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x204</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_MR">DBGU_MR</a></font></td><td><font size="-1">Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x208</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_IER">DBGU_IER</a></font></td><td><font size="-1">Interrupt Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x20C</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_IDR">DBGU_IDR</a></font></td><td><font size="-1">Interrupt Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x210</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_IMR">DBGU_IMR</a></font></td><td><font size="-1">Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x214</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_CSR">DBGU_CSR</a></font></td><td><font size="-1">Channel Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x218</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_RHR">DBGU_RHR</a></font></td><td><font size="-1">Receiver Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x21C</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_THR">DBGU_THR</a></font></td><td><font size="-1">Transmitter Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x220</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_BRGR">DBGU_BRGR</a></font></td><td><font size="-1">Baud Rate Generator Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x240</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_C1R">DBGU_C1R</a></font></td><td><font size="-1">Chip ID1 Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x244</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_C2R">DBGU_C2R</a></font></td><td><font size="-1">Chip ID2 Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x248</b></font></td><td><font size="-1"><a href="AT91RM9200_DBGU.html#DBGU_FNTR">DBGU_FNTR</a></font></td><td><font size="-1">Force NTRST Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x300</b></font></td><td><font size="-1">DBGU_RPR (<a href="AT91RM9200_PDC.html#PDC_RPR">PDC_RPR</a>)</font></td><td><font size="-1">Receive Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x304</b></font></td><td><font size="-1">DBGU_RCR (<a href="AT91RM9200_PDC.html#PDC_RCR">PDC_RCR</a>)</font></td><td><font size="-1">Receive Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x308</b></font></td><td><font size="-1">DBGU_TPR (<a href="AT91RM9200_PDC.html#PDC_TPR">PDC_TPR</a>)</font></td><td><font size="-1">Transmit Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x30C</b></font></td><td><font size="-1">DBGU_TCR (<a href="AT91RM9200_PDC.html#PDC_TCR">PDC_TCR</a>)</font></td><td><font size="-1">Transmit Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x310</b></font></td><td><font size="-1">DBGU_RNPR (<a href="AT91RM9200_PDC.html#PDC_RNPR">PDC_RNPR</a>)</font></td><td><font size="-1">Receive Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x314</b></font></td><td><font size="-1">DBGU_RNCR (<a href="AT91RM9200_PDC.html#PDC_RNCR">PDC_RNCR</a>)</font></td><td><font size="-1">Receive Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x318</b></font></td><td><font size="-1">DBGU_TNPR (<a href="AT91RM9200_PDC.html#PDC_TNPR">PDC_TNPR</a>)</font></td><td><font size="-1">Transmit Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x31C</b></font></td><td><font size="-1">DBGU_TNCR (<a href="AT91RM9200_PDC.html#PDC_TNCR">PDC_TNCR</a>)</font></td><td><font size="-1">Transmit Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x320</b></font></td><td><font size="-1">DBGU_PTCR (<a href="AT91RM9200_PDC.html#PDC_PTCR">PDC_PTCR</a>)</font></td><td><font size="-1">PDC Transfer Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x324</b></font></td><td><font size="-1">DBGU_PTSR (<a href="AT91RM9200_PDC.html#PDC_PTSR">PDC_PTSR</a>)</font></td><td><font size="-1">PDC Transfer Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x400</b></font></td><td><font size="-1">PIOA_PER (<a href="#PIO_PER">PIO_PER</a>)</font></td><td><font size="-1">PIO Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x404</b></font></td><td><font size="-1">PIOA_PDR (<a href="#PIO_PDR">PIO_PDR</a>)</font></td><td><font size="-1">PIO Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x408</b></font></td><td><font size="-1">PIOA_PSR (<a href="#PIO_PSR">PIO_PSR</a>)</font></td><td><font size="-1">PIO Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x410</b></font></td><td><font size="-1">PIOA_OER (<a href="#PIO_OER">PIO_OER</a>)</font></td><td><font size="-1">Output Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x414</b></font></td><td><font size="-1">PIOA_ODR (<a href="#PIO_ODR">PIO_ODR</a>)</font></td><td><font size="-1">Output Disable Registerr</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x418</b></font></td><td><font size="-1">PIOA_OSR (<a href="#PIO_OSR">PIO_OSR</a>)</font></td><td><font size="-1">Output Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x420</b></font></td><td><font size="-1">PIOA_IFER (<a href="#PIO_IFER">PIO_IFER</a>)</font></td><td><font size="-1">Input Filter Enable Register</font></td></tr>
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