<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="UDP_EPINT4"></a><b>UDP_EPINT4</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EPINT4">AT91C_UDP_EPINT4</a></font></td><td><b>Endpoint 4 Interrupt</b><br>0 = No Endpoint4 Interrupt pending.<br>1 = Endpoint4 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR4:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding USB_CSR4 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="UDP_EPINT5"></a><b>UDP_EPINT5</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EPINT5">AT91C_UDP_EPINT5</a></font></td><td><b>Endpoint 5 Interrupt</b><br>0 = No Endpoint5 Interrupt pending.<br>1 = Endpoint5 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR5:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding USB_CSR5 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="UDP_EPINT6"></a><b>UDP_EPINT6</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EPINT6">AT91C_UDP_EPINT6</a></font></td><td><b>Endpoint 6 Interrupt</b><br>0 = No Endpoint6 Interrupt pending.<br>1 = Endpoint6 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR6:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP6INT is a sticky bit. Interrupt remains valid until EP6INT is cleared by writing in the corresponding USB_CSR6 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="UDP_EPINT7"></a><b>UDP_EPINT7</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EPINT7">AT91C_UDP_EPINT7</a></font></td><td><b>Endpoint 7 Interrupt</b><br>0 = No Endpoint7 Interrupt pending.<br>1 = Endpoint7 Interrupt has been raised.<br>Several signals can generate this interrupt. The reason can be found by reading USB_CSR7:<br>RXSETUP set to 1<br>RX_DATA_BK0 set to 1<br>RX_DATA_BK1 set to 1<br>TXCOMP set to 1<br>STALLSENT set to 1<br>EP7INT is a sticky bit. Interrupt remains valid until EP7INT is cleared by writing in the corresponding USB_CSR7 bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="UDP_RXSUSP"></a><b>UDP_RXSUSP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_RXSUSP">AT91C_UDP_RXSUSP</a></font></td><td><b>USB Suspend Interrupt</b><br>0 = No USB Suspend Interrupt pending.<br>1 = USB Suspend Interrupt has been raised.<br>The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="UDP_RXRSM"></a><b>UDP_RXRSM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_RXRSM">AT91C_UDP_RXRSM</a></font></td><td><b>USB Resume Interrupt</b><br>0 = No USB Resume Interrupt pending.<br>1 =USB Resume Interrupt has been raised.<br>The USB device sets this bit when a USB resume signal is detected at its port.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="UDP_EXTRSM"></a><b>UDP_EXTRSM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EXTRSM">AT91C_UDP_EXTRSM</a></font></td><td><b>USB External Resume Interrupt</b><br>0 = No External Resume Interrupt pending.<br>1 = External Resume Interrupt has been raised.<br>This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="UDP_SOFINT"></a><b>UDP_SOFINT</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_SOFINT">AT91C_UDP_SOFINT</a></font></td><td><b>USB Start Of frame Interrupt</b><br>0 = No Start of Frame Interrupt pending.<br>1 = Start of Frame Interrupt has been raised.<br>This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="UDP_WAKEUP"></a><b>UDP_WAKEUP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_WAKEUP">AT91C_UDP_WAKEUP</a></font></td><td><b>USB Resume Interrupt</b><br>0 = No Wakeup Interrupt pending.<br>1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.</td></tr>
</null></table>
<a name="UDP_RSTEP"></a><h4><a href="#UDP">UDP</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> UDP_RSTEP  <i>Reset Endpoint Register</i></h4><ul><null><font size="-2"><li><b>UDP</b> <i><a href="AT91RM9200_h.html#AT91C_UDP_RSTEP">AT91C_UDP_RSTEP</a></i> 0xFFFB0028</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="UDP_EP0"></a><b>UDP_EP0</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EP0">AT91C_UDP_EP0</a></font></td><td><b>Reset Endpoint 0</b><br>0 = No effect.<br>1 = Reset endpoint.<br>Endpoint reset clears all flags in USB_CSR0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="UDP_EP1"></a><b>UDP_EP1</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EP1">AT91C_UDP_EP1</a></font></td><td><b>Reset Endpoint 1</b><br>0 = No effect.<br>1 = Reset endpoint.<br>Endpoint reset clears all flags in USB_CSR1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="UDP_EP2"></a><b>UDP_EP2</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EP2">AT91C_UDP_EP2</a></font></td><td><b>Reset Endpoint 2</b><br>0 = No effect.<br>1 = Reset endpoint.<br>Endpoint reset clears all flags in USB_CSR2.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="UDP_EP3"></a><b>UDP_EP3</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EP3">AT91C_UDP_EP3</a></font></td><td><b>Reset Endpoint 3</b><br>0 = No effect.<br>1 = Reset endpoint.<br>Endpoint reset clears all flags in USB_CSR3.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="UDP_EP4"></a><b>UDP_EP4</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EP4">AT91C_UDP_EP4</a></font></td><td><b>Reset Endpoint 4</b><br>0 = No effect.<br>1 = Reset endpoint.<br>Endpoint reset clears all flags in USB_CSR4.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="UDP_EP5"></a><b>UDP_EP5</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EP5">AT91C_UDP_EP5</a></font></td><td><b>Reset Endpoint 5</b><br>0 = No effect.<br>1 = Reset endpoint.<br>Endpoint reset clears all flags in USB_CSR5.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="UDP_EP6"></a><b>UDP_EP6</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EP6">AT91C_UDP_EP6</a></font></td><td><b>Reset Endpoint 6</b><br>0 = No effect.<br>1 = Reset endpoint.<br>Endpoint reset clears all flags in USB_CSR6.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="UDP_EP7"></a><b>UDP_EP7</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_EP7">AT91C_UDP_EP7</a></font></td><td><b>Reset Endpoint 7</b><br>0 = No effect.<br>1 = Reset endpoint.<br>Endpoint reset clears all flags in USB_CSR7.</td></tr>
</null></table>
<a name="UDP_CSR"></a><h4><a href="#UDP">UDP</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> UDP_CSR  <i>Endpoint Control and Status Register</i></h4><ul><null><font size="-2"><li><b>UDP</b> <i><a href="AT91RM9200_h.html#AT91C_UDP_CSR">AT91C_UDP_CSR</a></i> 0xFFFB0030</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="UDP_TXCOMP"></a><b>UDP_TXCOMP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_TXCOMP">AT91C_UDP_TXCOMP</a></font></td><td><b>Generates an IN packet with data previously written in the DPR</b><br>This flag generates an interrupt while it is set to one.<br>Write (Cleared by the firmware)<br>0 = Clear the flag, clear the interrupt.<br>1 = No effect.<br>Read (Set by the USB peripheral)<br>0 = Data IN transaction has not been acknowledged by the Host.<br>1 = Data IN transaction is achieved, acknowledged by the Host.<br>After having issued a Data IN transaction setting TXPKTREADY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="UDP_RX_DATA_BK0"></a><b>UDP_RX_DATA_BK0</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_RX_DATA_BK0">AT91C_UDP_RX_DATA_BK0</a></font></td><td><b>Receive Data Bank 0</b><br>This flag generates an interrupt while it is set to one.<br>Write (Cleared by the firmware)<br>0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0.<br>1 = No effect.<br>Read (Set by the USB peripheral)<br>0 = No data packet has been received in the FIFO's Bank 0<br>1 = A data packet has been received, it has been stored in the FIFO's Bank 0.<br>When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the USB_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="UDP_RXSETUP"></a><b>UDP_RXSETUP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_RXSETUP">AT91C_UDP_RXSETUP</a></font></td><td><b>Sends STALL to the Host (Control endpoints)</b><br>This flag generates an interrupt while it is set to one.<br>Read<br>0 = No setup packet available.<br>1 = A setup data packet has been sent by the host and is available in the FIFO.<br>Write<br>0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO.<br>1 = No effect.<br>This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and success-fully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the USB_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware.<br>Ensuing Data OUT transactions will not be accepted while RXSETUP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="UDP_ISOERROR"></a><b>UDP_ISOERROR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_ISOERROR">AT91C_UDP_ISOERROR</a></font></td><td><b>Isochronous error (Isochronous endpoints)</b><br>A CRC error has been detected in an isochronous transfer<br>Read<br>0 = No error in the previous isochronous transfer.<br>1 = CRC error has been detected, data available in the FIFO are corrupted.<br>Write<br>0 = reset the ISOERROR flag, clear the interrupt.<br>1 = No effect.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="UDP_TXPKTRDY"></a><b>UDP_TXPKTRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_TXPKTRDY">AT91C_UDP_TXPKTRDY</a></font></td><td><b>Transmit Packet Ready</b><br>This flag is cleared by the USB device.<br>This flag is set by the USB device firmware.<br>Read<br>0 = Data values can be written in the FIFO.<br>1 = Data values can not be written in the FIFO.<br>Write<br>0 = No effect.<br>1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent.<br>This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTREADY is cleared. Transfer to the FIFO is done by writing in the USB_FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTREADY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="UDP_FORCESTALL"></a><b>UDP_FORCESTALL</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_FORCESTALL">AT91C_UDP_FORCESTALL</a></font></td><td><b>Force Stall (used by Control, Bulk and Isochronous endpoints).</b><br>Write-only<br>0 = No effect.<br>1 = Send STALL to the host.<br>Please refer to chapters 8.4.4 and 9.4.5 of the Universal Serial Bus Specification, Rev. 1.1 to get more information on the STALL handshake.<br>Control endpoints: during the data stage and status stage, this indicates that the microcontroller can not complete the request.<br>Bulk and interrupt endpoints: notify the host that the endpoint is halted.<br>The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="UDP_RX_DATA_BK1"></a><b>UDP_RX_DATA_BK1</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_RX_DATA_BK1">AT91C_UDP_RX_DATA_BK1</a></font></td><td><b>Receive Data Bank 1 (only used by endpoints with ping-pong attributes).</b><br>This flag generates an interrupt while it is set to one.<br>Write (Cleared by the firmware)<br>0 = Notify USB device that data have been read in the FIFO&#146;s Bank 1.<br>1 = No effect.<br>Read (Set by the USB peripheral)<br>0 = No data packet has been received in the FIFO's Bank 1.<br>1 = A data packet has been received, it has been stored in FIFO's Bank 1.<br>When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through USB_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clear-ing RX_DATA_BK1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="UDP_DIR"></a><b>UDP_DIR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_UDP_DIR">AT91C_UDP_DIR</a></font></td><td><b>Transfer Direction</b><br>0 = Allow Data OUT transactions in the control data stage.<br>1 = Enable Data IN transactions in the control data stage.<br>Please refer to Chapter 8.5.2 of the Universal Serial Bus Specification, Rev. 1.1 to get more information on the control data stage.<br>This bit must be set after the end of the setup stage. According to the request sent in the setup data packet, the data stage<br>will either be a device to host (DIR = 1) or host to device (DIR = 0) data tr