<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_CfgDirectDrive">AT91F_PIO_CfgDirectDrive</a></b></font></td><td><font size="-1">Enable direct drive on PIO</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_IsSet">AT91F_PIO_IsSet</a></b></font></td><td><font size="-1">Test if PIO is Set</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_IsInterruptMasked">AT91F_PIO_IsInterruptMasked</a></b></font></td><td><font size="-1">Test if PIO Interrupt is Masked </font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_MultiDriverDisable">AT91F_PIO_MultiDriverDisable</a></b></font></td><td><font size="-1">Multi Driver Disable PIO</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_IsInterruptSet">AT91F_PIO_IsInterruptSet</a></b></font></td><td><font size="-1">Test if PIO Interrupt is Set</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_OutputEnable">AT91F_PIO_OutputEnable</a></b></font></td><td><font size="-1">Output Enable PIO</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_InputFilterDisable">AT91F_PIO_InputFilterDisable</a></b></font></td><td><font size="-1">Input Filter Disable PIO</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_IsOutputDataStatusSet">AT91F_PIO_IsOutputDataStatusSet</a></b></font></td><td><font size="-1">Test if PIO Output Data Status is Set </font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_CfgInputFilter">AT91F_PIO_CfgInputFilter</a></b></font></td><td><font size="-1">Enable input filter on input PIO</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_CfgPeriph">AT91F_PIO_CfgPeriph</a></b></font></td><td><font size="-1">Enable pins to be drived by peripheral</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_IsCfgPullupStatusSet">AT91F_PIO_IsCfgPullupStatusSet</a></b></font></td><td><font size="-1">Test if PIO Configuration Pullup Status is Set</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_GetStatus">AT91F_PIO_GetStatus</a></b></font></td><td><font size="-1">Return PIO Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_ClearOutput">AT91F_PIO_ClearOutput</a></b></font></td><td><font size="-1">Set to 0 output PIO</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_IsInputSet">AT91F_PIO_IsInputSet</a></b></font></td><td><font size="-1">Test if PIO is input flag is active</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_IsOuputSet">AT91F_PIO_IsOuputSet</a></b></font></td><td><font size="-1">Test if PIO Output is Set</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_CfgOpendrain">AT91F_PIO_CfgOpendrain</a></b></font></td><td><font size="-1">Configure PIO in open drain</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_CfgPullup">AT91F_PIO_CfgPullup</a></b></font></td><td><font size="-1">Enable pullup on PIO</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_GetInterruptMaskStatus">AT91F_PIO_GetInterruptMaskStatus</a></b></font></td><td><font size="-1">Return PIO Interrupt Mask Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91RM9200_h.html#AT91F_PIO_ForceOutput">AT91F_PIO_ForceOutput</a></b></font></td><td><font size="-1">Force output when Direct drive option is enabled</font></td></tr>
</null></table></null><h2>PIO Register Description</h2>
<null><a name="PIO_PER"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_PER  <i>PIO Enable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_PER">AT91C_PIOD_PER</a></i> 0xFFFFFA00</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_PER">AT91C_PIOC_PER</a></i> 0xFFFFF800</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_PER">AT91C_PIOB_PER</a></i> 0xFFFFF600</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_PER">AT91C_PIOA_PER</a></i> 0xFFFFF400</font></null></ul><br>This register is used to enable control of individual pins by the PIO controller rather than by an internally connected periph-eral. When the PIO is enabled, the Data to Peripheral (d_to_periph_a or d_to_periph_b) signal is held at logic zero. The register is programmed as follows:<br>1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).<br>0 = No effect.<a name="PIO_PDR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_PDR  <i>PIO Disable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_PDR">AT91C_PIOD_PDR</a></i> 0xFFFFFA04</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_PDR">AT91C_PIOC_PDR</a></i> 0xFFFFF804</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_PDR">AT91C_PIOB_PDR</a></i> 0xFFFFF604</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_PDR">AT91C_PIOA_PDR</a></i> 0xFFFFF404</font></null></ul><br>This register is used to disable control of individual pins by the PIO controller. When PIO control is disabled, the peripheral function (if any) connected to the I/O channel is enabled to control the corresponding pin. The register is programmed as follows:<br>1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).<br>0 = No effect.<a name="PIO_PSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_PSR  <i>PIO Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_PSR">AT91C_PIOD_PSR</a></i> 0xFFFFFA08</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_PSR">AT91C_PIOC_PSR</a></i> 0xFFFFF808</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_PSR">AT91C_PIOB_PSR</a></i> 0xFFFFF608</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_PSR">AT91C_PIOA_PSR</a></i> 0xFFFFF408</font></null></ul><br>This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or dis-abled.The register reads as follows:<br>1 = PIO is active on the corresponding line (peripheral is inactive).<br>0 = PIO is inactive on the corresponding line (peripheral is active).<a name="PIO_OER"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_OER  <i>Output Enable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_OER">AT91C_PIOD_OER</a></i> 0xFFFFFA10</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_OER">AT91C_PIOC_OER</a></i> 0xFFFFF810</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_OER">AT91C_PIOB_OER</a></i> 0xFFFFF610</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_OER">AT91C_PIOA_OER</a></i> 0xFFFFF410</font></null></ul><br>This register is used to enable PIO output drivers. If the pin is driven by an internally connected peripheral, PIO_OER has no effect on the pin, but the information is stored. The register is programmed as follows:<br>1 = Enables the PIO output on the corresponding pin.<br>0 = No effect.<a name="PIO_ODR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_ODR  <i>Output Disable Registerr</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_ODR">AT91C_PIOD_ODR</a></i> 0xFFFFFA14</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_ODR">AT91C_PIOC_ODR</a></i> 0xFFFFF814</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_ODR">AT91C_PIOB_ODR</a></i> 0xFFFFF614</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_ODR">AT91C_PIOA_ODR</a></i> 0xFFFFF414</font></null></ul><br>This register is used to disable PIO output drivers. If the pin is driven by the peripheral, this has no effect on the pin, but the information is stored. The register is programmed as follows:<br>0 = No effect.<br>1 = Disables the PIO output on the corresponding pin.<a name="PIO_OSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_OSR  <i>Output Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_OSR">AT91C_PIOD_OSR</a></i> 0xFFFFFA18</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_OSR">AT91C_PIOC_OSR</a></i> 0xFFFFF818</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_OSR">AT91C_PIOB_OSR</a></i> 0xFFFFF618</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_OSR">AT91C_PIOA_OSR</a></i> 0xFFFFF418</font></null></ul><br>This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows:<br>0 = The corresponding PIO is input on this line.<br>1 = The corresponding PIO is output on this line.<a name="PIO_IFER"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_IFER  <i>Input Filter Enable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_IFER">AT91C_PIOD_IFER</a></i> 0xFFFFFA20</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_IFER">AT91C_PIOC_IFER</a></i> 0xFFFFF820</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_IFER">AT91C_PIOB_IFER</a></i> 0xFFFFF620</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_IFER">AT91C_PIOA_IFER</a></i> 0xFFFFF420</font></null></ul><br>This register is used to enable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is programmed as follows:<br>0 = No effect.<br>1 = Enables the glitch filter on the corresponding pin.<a name="PIO_IFDR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_IFDR  <i>Input Filter Disable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_IFDR">AT91C_PIOD_IFDR</a></i> 0xFFFFFA24</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_IFDR">AT91C_PIOC_IFDR</a></i> 0xFFFFF824</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_IFDR">AT91C_PIOB_IFDR</a></i> 0xFFFFF624</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_IFDR">AT91C_PIOA_IFDR</a></i> 0xFFFFF424</font></null></ul><br>This register is used to disable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is pro-grammed as follows:<br>0 = No effect.<br>1 = Disables the glitch filter on the corresponding pin.<a name="PIO_IFSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_IFSR  <i>Input Filter Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_IFSR">AT91C_PIOD_IFSR</a></i> 0xFFFFFA28</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_IFSR">AT91C_PIOC_IFSR</a></i> 0xFFFFF828</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_IFSR">AT91C_PIOB_IFSR</a></i> 0xFFFFF628</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_IFSR">AT91C_PIOA_IFSR</a></i> 0xFFFFF428</font></null></ul><br>This register indicates which pins have glitch filters selected. It is updated when PIO outputs are enabled or disabled by writing to PIO_IFER or PIO_IFDR.<br>0 = Filter is not selected on the corresponding input.<br>1 = Filter is selected on the corresponding input (peripheral and PIO).<a name="PIO_SODR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_SODR  <i>Set Output Data Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_SODR">AT91C_PIOD_SODR</a></i> 0xFFFFFA30</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_SODR">AT91C_PIOC_SODR</a></i> 0xFFFFF830</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_SODR">AT91C_PIOB_SODR</a></i> 0xFFFFF630</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_SODR">AT91C_PIOA_SODR</a></i> 0xFFFFF430</font></null></ul><br>This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored.<br>0 = No effect.<br>1 = PIO output data on the corresponding pin is set.<a name="PIO_CODR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_CODR  <i>Clear Output Data Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_CODR">AT91C_PIOD_CODR</a></i> 0xFFFFFA34</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_CODR">AT91C_PIOC_CODR</a></i> 0xFFFFF834</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_CODR">AT91C_PIOB_CODR</a></i> 0xFFFFF634</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_CODR">AT91C_PIOA_CODR</a></i> 0xFFFFF434</font></null></ul><br>This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored.<br>0 = No effect.<br>1 = PIO output data on the corresponding pin is cleared.<a name="PIO_ODSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_ODSR  <i>Output Data Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_ODSR">AT91C_PIOD_ODSR</a></i> 0xFFFFFA38</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_ODSR">AT91C_PIOC_ODSR</a></i> 0xFFFFF838</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_ODSR">AT91C_PIOB_ODSR</a></i> 0xFFFFF638</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_ODSR">AT91C_PIOA_ODSR</a></i> 0xFFFFF438</font></null></ul><br>This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effec-tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output.<br>0 = The output data for the corresponding line is programmed to 0.<br>1 = The output data for the corresponding line is programmed to 1.<a name="PIO_PDSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_PDSR  <i>Pin Data Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_PDSR">AT91C_PIOD_PDSR</a></i> 0xFFFFFA3C</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_PDSR">AT91C_PIOC_PDSR</a></i> 0xFFFFF83C</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_PDSR">AT91C_PIOB_PDSR</a></i> 0xFFFFF63C</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_PDSR">AT91C_PIOA_PDSR</a></i> 0xFFFFF43C</font></null></ul><br>This register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows:<br>1 = The corresponding pin is at logic 1.<br>0 = The corresponding pin is at logic 0.<a name="PIO_IER"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_IER">AT91C_PIOD_IER</a></i> 0xFFFFFA40</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_IER">AT91C_PIOC_IER</a></i> 0xFFFFF840</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_IER">AT91C_PIOB_IER</a></i> 0xFFFFF640</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_IER">AT91C_PIOA_IER</a></i> 0xFFFFF440</font></null></ul><br>This register is used to enable PIO interrupts generated by the corresponding pins; logic level changes are detected and stored in the Interrupt Status Register (PIO_ISR). Enabled interrupts will be generated whether the PIO is enabled or not. The register is programmed as follows:<br>1 = Enables an interrupt when a change of logic level is detected on the corresponding pin.<br>0 = No effect.<a name="PIO_IDR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_IDR">AT91C_PIOD_IDR</a></i> 0xFFFFFA44</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_IDR">AT91C_PIOC_IDR</a></i> 0xFFFFF844</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_IDR">AT91C_PIOB_IDR</a></i> 0xFFFFF644</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_IDR">AT91C_PIOA_IDR</a></i> 0xFFFFF444</font></null></ul><br>This register is used to enable PIO interrupts generated by the corresponding pins; logic level changes are detected and stored in the Interrupt Status Register (PIO_ISR). Enabled interrupts will be generated whether the PIO is enabled or not. The register is programmed as follows:<br>1 = Enables an interrupt when a change of logic level is detected on the corresponding pin.<br>0 = No effect.<a name="PIO_IMR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_IMR">AT91C_PIOD_IMR</a></i> 0xFFFFFA48</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_IMR">AT91C_PIOC_IMR</a></i> 0xFFFFF848</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_IMR">AT91C_PIOB_IMR</a></i> 0xFFFFF648</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_IMR">AT91C_PIOA_IMR</a></i> 0xFFFFF448</font></null></ul><br>This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR. The register reads as follows:<br>1 = Interrupt is enabled from the corresponding pin.<br>0 = Interrupt is disabled from the corresponding pin.<a name="PIO_ISR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_ISR  <i>Interrupt Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_ISR">AT91C_PIOD_ISR</a></i> 0xFFFFFA4C</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_ISR">AT91C_PIOC_ISR</a></i> 0xFFFFF84C</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_ISR">AT91C_PIOB_ISR</a></i> 0xFFFFF64C</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_ISR">AT91C_PIOA_ISR</a></i> 0xFFFFF44C</font></null></ul><br>This register indicates, for each pin, when a logic level change has been detected (rising or falling edge). This is valid whether the PIO is selected for the pin or not and whether the pin is an input or output. The register is reset to zero following a read, as well as at reset. The register reads as follows:<br>1 = At least one change has been detected on the corresponding pin since the register was last read or since reset.<br>0 = No change has been detected on the corresponding pin since the register was last read or since reset.<a name="PIO_MDER"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_MDER  <i>Multi-driver Enable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_MDER">AT91C_PIOD_MDER</a></i> 0xFFFFFA50</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_MDER">AT91C_PIOC_MDER</a></i> 0xFFFFF850</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_MDER">AT91C_PIOB_MDER</a></i> 0xFFFFF650</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_MDER">AT91C_PIOA_MDER</a></i> 0xFFFFF450</font></null></ul><br>This register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows:<br>1 = The corresponding pin is at logic 1.<br>0 = The corresponding pin is at logic 0.<a name="PIO_MDDR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_MDDR  <i>Multi-driver Disable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_MDDR">AT91C_PIOD_MDDR</a></i> 0xFFFFFA54</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_MDDR">AT91C_PIOC_MDDR</a></i> 0xFFFFF854</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_MDDR">AT91C_PIOB_MDDR</a></i> 0xFFFFF654</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_MDDR">AT91C_PIOA_MDDR</a></i> 0xFFFFF454</font></null></ul><br>This register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows:<br>1 = The corresponding pin is at logic 1.<br>0 = The corresponding pin is at logic 0.<a name="PIO_MDSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_MDSR  <i>Multi-driver Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_MDSR">AT91C_PIOD_MDSR</a></i> 0xFFFFFA58</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_MDSR">AT91C_PIOC_MDSR</a></i> 0xFFFFF858</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_MDSR">AT91C_PIOB_MDSR</a></i> 0xFFFFF658</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_MDSR">AT91C_PIOA_MDSR</a></i> 0xFFFFF458</font></null></ul><br>This register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows:<br>1 = The corresponding pin is at logic 1.<br>0 = The corresponding pin is at logic 0.<a name="PIO_PPUDR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_PPUDR  <i>Pull-up Disable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_PPUDR">AT91C_PIOD_PPUDR</a></i> 0xFFFFFA60</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_PPUDR">AT91C_PIOC_PPUDR</a></i> 0xFFFFF860</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_PPUDR">AT91C_PIOB_PPUDR</a></i> 0xFFFFF660</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_PPUDR">AT91C_PIOA_PPUDR</a></i> 0xFFFFF460</font></null></ul><br>0 = No effect.<br>1 = Input pad pull-up is disabled.<a name="PIO_PPUER"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_PPUER  <i>Pull-up Enable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_PPUER">AT91C_PIOD_PPUER</a></i> 0xFFFFFA64</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_PPUER">AT91C_PIOC_PPUER</a></i> 0xFFFFF864</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_PPUER">AT91C_PIOB_PPUER</a></i> 0xFFFFF664</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_PPUER">AT91C_PIOA_PPUER</a></i> 0xFFFFF464</font></null></ul><br>0 = No effect.<br>1 = Input pad pull-up is enabled.<a name="PIO_PPUSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_PPUSR  <i>Pad Pull-up Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_PPUSR">AT91C_PIOD_PPUSR</a></i> 0xFFFFFA68</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_PPUSR">AT91C_PIOC_PPUSR</a></i> 0xFFFFF868</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_PPUSR">AT91C_PIOB_PPUSR</a></i> 0xFFFFF668</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_PPUSR">AT91C_PIOA_PPUSR</a></i> 0xFFFFF468</font></null></ul><br>0 = Input pad pull-up is enabled.<br>1 = Input pad pull-up is disabled with an active low level pull-up control pin.<a name="PIO_ASR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_ASR  <i>Select A Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_ASR">AT91C_PIOD_ASR</a></i> 0xFFFFFA70</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_ASR">AT91C_PIOC_ASR</a></i> 0xFFFFF870</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_ASR">AT91C_PIOB_ASR</a></i> 0xFFFFF670</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_ASR">AT91C_PIOA_ASR</a></i> 0xFFFFF470</font></null></ul><br>1 = Select peripheral A.<br>0 = No effect.<a name="PIO_BSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_BSR  <i>Select B Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_BSR">AT91C_PIOD_BSR</a></i> 0xFFFFFA74</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_BSR">AT91C_PIOC_BSR</a></i> 0xFFFFF874</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_BSR">AT91C_PIOB_BSR</a></i> 0xFFFFF674</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_BSR">AT91C_PIOA_BSR</a></i> 0xFFFFF474</font></null></ul><br>1 = Select peripheral B.<br>0 = No effect.<a name="PIO_ABSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_ABSR  <i>AB Select Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_ABSR">AT91C_PIOD_ABSR</a></i> 0xFFFFFA78</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_ABSR">AT91C_PIOC_ABSR</a></i> 0xFFFFF878</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_ABSR">AT91C_PIOB_ABSR</a></i> 0xFFFFF678</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_ABSR">AT91C_PIOA_ABSR</a></i> 0xFFFFF478</font></null></ul><br>0 = Peripheral A Selected.<br>1 = Peripheral B Selected.<a name="PIO_OWER"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_OWER  <i>Output Write Enable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_OWER">AT91C_PIOD_OWER</a></i> 0xFFFFFAA0</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_OWER">AT91C_PIOC_OWER</a></i> 0xFFFFF8A0</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_OWER">AT91C_PIOB_OWER</a></i> 0xFFFFF6A0</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_OWER">AT91C_PIOA_OWER</a></i> 0xFFFFF4A0</font></null></ul><br>1 = Enables the possibility to write directly to PIO_ODSR Register.<br>0 = No effect.<a name="PIO_OWDR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_OWDR  <i>Output Write Disable Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_OWDR">AT91C_PIOD_OWDR</a></i> 0xFFFFFAA4</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_OWDR">AT91C_PIOC_OWDR</a></i> 0xFFFFF8A4</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_OWDR">AT91C_PIOB_OWDR</a></i> 0xFFFFF6A4</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_OWDR">AT91C_PIOA_OWDR</a></i> 0xFFFFF4A4</font></null></ul><br>1 = Disables the possibility to write directly to PIO_ODSR Register.<br>0 = No effect.<a name="PIO_OWSR"></a><h4><a href="#PIO">PIO</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> PIO_OWSR  <i>Output Write Status Register</i></h4><ul><null><font size="-2"><li><b>PIOD</b> <i><a href="AT91RM9200_h.html#AT91C_PIOD_OWSR">AT91C_PIOD_OWSR</a></i> 0xFFFFFAA8</font><font size="-2"><li><b>PIOC</b> <i><a href="AT91RM9200_h.html#AT91C_PIOC_OWSR">AT91C_PIOC_OWSR</a></i> 0xFFFFF8A8</font><font size="-2"><li><b>PIOB</b> <i><a href="AT91RM9200_h.html#AT91C_PIOB_OWSR">AT91C_PIOB_OWSR</a></i> 0xFFFFF6A8</font><font size="-2"><li><b>PIOA</b> <i><a href="AT91RM9200_h.html#AT91C_PIOA_OWSR">AT91C_PIOA_OWSR</a></i> 0xFFFFF4A8</font></null></ul><br>1 = Direct write to PIO_ODSR is enabled.<br>0 = Direct write to PIO_ODSR is disabled.</null><hr></html>