<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TWI_MSDIS"></a><b>TWI_MSDIS</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_MSDIS">AT91C_TWI_MSDIS</a></font></td><td><b>TWI Master Transfer Disabled</b><br>0: No effect.<br>1: The master data transfer is disabled, all pending data is transmitted. The shifter and holding character (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TWI_SVEN"></a><b>TWI_SVEN</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVEN">AT91C_TWI_SVEN</a></font></td><td><b>TWI Slave Transfer Enabled</b><br>0: No effect.<br>1: If SVDIS = 0, the slave data transfer is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TWI_SVDIS"></a><b>TWI_SVDIS</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVDIS">AT91C_TWI_SVDIS</a></font></td><td><b>TWI Slave Transfer Disabled</b><br>0: No effect.<br>1: The slave data transfer is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_SWRST"></a><b>TWI_SWRST</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SWRST">AT91C_TWI_SWRST</a></font></td><td><b>Software Reset</b><br>0: No effect.<br>1: Equivalent to a system reset.</td></tr>
</null></table>
<a name="TWI_MMR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_MMR  <i>Master Mode Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_MMR">AT91C_TWI_MMR</a></i> 0xFFFB8004</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..8</td><td align="CENTER"><a name="TWI_IADRSZ"></a><b>TWI_IADRSZ</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_IADRSZ">AT91C_TWI_IADRSZ</a></font></td><td><b>Internal Device Address Size</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="TWI_IADRSZ_NO"></a><b>TWI_IADRSZ_NO</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_TWI_IADRSZ_NO">AT91C_TWI_IADRSZ_NO</a></font></td><td><br>No internal device address</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="TWI_IADRSZ_1_BYTE"></a><b>TWI_IADRSZ_1_BYTE</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_TWI_IADRSZ_1_BYTE">AT91C_TWI_IADRSZ_1_BYTE</a></font></td><td><br>One-byte internal device address</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="TWI_IADRSZ_2_BYTE"></a><b>TWI_IADRSZ_2_BYTE</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_TWI_IADRSZ_2_BYTE">AT91C_TWI_IADRSZ_2_BYTE</a></font></td><td><br>Two-byte internal device address</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="TWI_IADRSZ_3_BYTE"></a><b>TWI_IADRSZ_3_BYTE</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_TWI_IADRSZ_3_BYTE">AT91C_TWI_IADRSZ_3_BYTE</a></font></td><td><br>Three-byte internal device address</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="TWI_MREAD"></a><b>TWI_MREAD</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_MREAD">AT91C_TWI_MREAD</a></font></td><td><b>Master Read Direction</b><br>0: Master write direction<br>1: Master read direction</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..16</td><td align="CENTER"><a name="TWI_DADR"></a><b>TWI_DADR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_DADR">AT91C_TWI_DADR</a></font></td><td><b>Device Address</b><br>The device address is used in master mode to access slave devices in read or write mode.</td></tr>
</null></table>
<a name="TWI_SMR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_SMR  <i>Slave Mode Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_SMR">AT91C_TWI_SMR</a></i> 0xFFFB8008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">22..16</td><td align="CENTER"><a name="TWI_SADR"></a><b>TWI_SADR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SADR">AT91C_TWI_SADR</a></font></td><td><b>Slave Device Address</b><br>The slave device address is used in slave mode in order to be accessed by master devices in read or write mode.</td></tr>
</null></table>
<a name="TWI_IADR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_IADR  <i>Internal Address Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_IADR">AT91C_TWI_IADR</a></i> 0xFFFB800C</font></null></ul><br>0, 1, 2 or 3 bytes depending on IADRSZ<a name="TWI_CWGR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_CWGR  <i>Clock Waveform Generator Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_CWGR">AT91C_TWI_CWGR</a></i> 0xFFFB8010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="TWI_CLDIV"></a><b>TWI_CLDIV</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_CLDIV">AT91C_TWI_CLDIV</a></font></td><td><b>Clock Low Divider</b><br>The SCL low period is defined as follows: Tlow = (CLDIV * 2 ^CKDIV) + 4) * Tmclk</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..8</td><td align="CENTER"><a name="TWI_CHDIV"></a><b>TWI_CHDIV</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_CHDIV">AT91C_TWI_CHDIV</a></font></td><td><b>Clock High Divider</b><br>The SCL high period is defined as follows: Thigh = (CLDIV * 2 ^CKDIV) + 4) * Tmclk</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18..16</td><td align="CENTER"><a name="TWI_CKDIV"></a><b>TWI_CKDIV</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_CKDIV">AT91C_TWI_CKDIV</a></font></td><td><b>Clock Divider</b><br>The CKDIV is used to increase both SCL high and low periods.</td></tr>
</null></table>
<a name="TWI_SR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_SR  <i>Status Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_SR">AT91C_TWI_SR</a></i> 0xFFFB8020</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_TXCOMP"></a><b>TWI_TXCOMP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_TXCOMP">AT91C_TWI_TXCOMP</a></font></td><td><b>Transmission Completed</b><br>0: In master, during the length of the current frame. In slave, from START received to STOP received.<br>1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in theTWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_TXRDY"></a><b>TWI_TXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_TXRDY">AT91C_TWI_TXRDY</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.<br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TWI_SVREAD"></a><b>TWI_SVREAD</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVREAD">AT91C_TWI_SVREAD</a></font></td><td><b>Slave Read</b><br>0: Slave accessed in write direction, valid only if SVACC is set.<br>1: Slave accessed in read direction, valid only if SVACC is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TWI_SVACC"></a><b>TWI_SVACC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVACC">AT91C_TWI_SVACC</a></font></td><td><b>Slave Access</b><br>0: No slave access<br>1: The device address received matches the SADR register. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TWI_GCACC"></a><b>TWI_GCACC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_GCACC">AT91C_TWI_GCACC</a></font></td><td><b>General Call Access</b><br>0: No slave access<br>1: The received device address matches the general call address. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error</b><br>0: TWI_RHR has not been loaded while RXRDY was set<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_UNRE"></a><b>TWI_UNRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_UNRE">AT91C_TWI_UNRE</a></font></td><td><b>Underrun Error</b><br>0: No underrun error<br>1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TWI_NACK"></a><b>TWI_NACK</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_NACK">AT91C_TWI_NACK</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="TWI_ARBLST"></a><b>TWI_ARBLST</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_ARBLST">AT91C_TWI_ARBLST</a></font></td><td><b>Arbitration Lost</b><br>0: Arbitration win<br>1: Arbitration lost; another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. Reset by read in TWI_SR.</td></tr>
</null></table>
<a name="TWI_IER"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_IER">AT91C_TWI_IER</a></i> 0xFFFB8024</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_TXCOMP"></a><b>TWI_TXCOMP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_TXCOMP">AT91C_TWI_TXCOMP</a></font></td><td><b>Transmission Completed</b><br>0: In master, during the length of the current frame. In slave, from START received to STOP received.<br>1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in theTWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_TXRDY"></a><b>TWI_TXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_TXRDY">AT91C_TWI_TXRDY</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.<br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>