AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address
AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address
AT91C_TWI_MREAD           EQU (0x1:SHL:12) ;- (TWI) Master Read Direction
AT91C_TWI_DADR            EQU (0x7F:SHL:16) ;- (TWI) Device Address
;- -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
AT91C_TWI_SADR            EQU (0x7F:SHL:16) ;- (TWI) Slave Device Address
;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
AT91C_TWI_CLDIV           EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider
AT91C_TWI_CHDIV           EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider
AT91C_TWI_CKDIV           EQU (0x7:SHL:16) ;- (TWI) Clock Divider
;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
AT91C_TWI_TXCOMP          EQU (0x1:SHL:0) ;- (TWI) Transmission Completed
AT91C_TWI_RXRDY           EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY
AT91C_TWI_TXRDY           EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY
AT91C_TWI_SVREAD          EQU (0x1:SHL:3) ;- (TWI) Slave Read
AT91C_TWI_SVACC           EQU (0x1:SHL:4) ;- (TWI) Slave Access
AT91C_TWI_GCACC           EQU (0x1:SHL:5) ;- (TWI) General Call Access
AT91C_TWI_OVRE            EQU (0x1:SHL:6) ;- (TWI) Overrun Error
AT91C_TWI_UNRE            EQU (0x1:SHL:7) ;- (TWI) Underrun Error
AT91C_TWI_NACK            EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged
AT91C_TWI_ARBLST          EQU (0x1:SHL:9) ;- (TWI) Arbitration Lost
;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_MCI
MCI_CR          #  4 ;- MCI Control Register
MCI_MR          #  4 ;- MCI Mode Register
MCI_DTOR        #  4 ;- MCI Data Timeout Register
MCI_SDCR        #  4 ;- MCI SD Card Register
MCI_ARGR        #  4 ;- MCI Argument Register
MCI_CMDR        #  4 ;- MCI Command Register
                #  8 ;- Reserved
MCI_RSPR        # 16 ;- MCI Response Register
MCI_RDR         #  4 ;- MCI Receive Data Register
MCI_TDR         #  4 ;- MCI Transmit Data Register
                #  8 ;- Reserved
MCI_SR          #  4 ;- MCI Status Register
MCI_IER         #  4 ;- MCI Interrupt Enable Register
MCI_IDR         #  4 ;- MCI Interrupt Disable Register
MCI_IMR         #  4 ;- MCI Interrupt Mask Register
                # 176 ;- Reserved
MCI_RPR         #  4 ;- Receive Pointer Register
MCI_RCR         #  4 ;- Receive Counter Register
MCI_TPR         #  4 ;- Transmit Pointer Register
MCI_TCR         #  4 ;- Transmit Counter Register
MCI_RNPR        #  4 ;- Receive Next Pointer Register
MCI_RNCR        #  4 ;- Receive Next Counter Register
MCI_TNPR        #  4 ;- Transmit Next Pointer Register
MCI_TNCR        #  4 ;- Transmit Next Counter Register
MCI_PTCR        #  4 ;- PDC Transfer Control Register
MCI_PTSR        #  4 ;- PDC Transfer Status Register
;- -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
AT91C_MCI_MCIEN           EQU (0x1:SHL:0) ;- (MCI) Multimedia Interface Enable
AT91C_MCI_MCIDIS          EQU (0x1:SHL:1) ;- (MCI) Multimedia Interface Disable
AT91C_MCI_PWSEN           EQU (0x1:SHL:2) ;- (MCI) Power Save Mode Enable
AT91C_MCI_PWSDIS          EQU (0x1:SHL:3) ;- (MCI) Power Save Mode Disable
;- -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
AT91C_MCI_CLKDIV          EQU (0x1:SHL:0) ;- (MCI) Clock Divider
AT91C_MCI_PWSDIV          EQU (0x1:SHL:8) ;- (MCI) Power Saving Divider
AT91C_MCI_PDCPADV         EQU (0x1:SHL:14) ;- (MCI) PDC Padding Value
AT91C_MCI_PDCMODE         EQU (0x1:SHL:15) ;- (MCI) PDC Oriented Mode
AT91C_MCI_BLKLEN          EQU (0x1:SHL:18) ;- (MCI) Data Block Length
;- -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
AT91C_MCI_DTOCYC          EQU (0x1:SHL:0) ;- (MCI) Data Timeout Cycle Number
AT91C_MCI_DTOMUL          EQU (0x7:SHL:4) ;- (MCI) Data Timeout Multiplier
AT91C_MCI_DTOMUL_1        EQU (0x0:SHL:4) ;- (MCI) DTOCYC x 1
AT91C_MCI_DTOMUL_16       EQU (0x1:SHL:4) ;- (MCI) DTOCYC x 16
AT91C_MCI_DTOMUL_128      EQU (0x2:SHL:4) ;- (MCI) DTOCYC x 128
AT91C_MCI_DTOMUL_256      EQU (0x3:SHL:4) ;- (MCI) DTOCYC x 256
AT91C_MCI_DTOMUL_1024     EQU (0x4:SHL:4) ;- (MCI) DTOCYC x 1024
AT91C_MCI_DTOMUL_4096     EQU (0x5:SHL:4) ;- (MCI) DTOCYC x 4096
AT91C_MCI_DTOMUL_65536    EQU (0x6:SHL:4) ;- (MCI) DTOCYC x 65536
AT91C_MCI_DTOMUL_1048576  EQU (0x7:SHL:4) ;- (MCI) DTOCYC x 1048576
;- -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
AT91C_MCI_SCDSEL          EQU (0x1:SHL:0) ;- (MCI) SD Card Selector
AT91C_MCI_SCDBUS          EQU (0x1:SHL:7) ;- (MCI) SD Card Bus Width
;- -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
AT91C_MCI_CMDNB           EQU (0x1F:SHL:0) ;- (MCI) Command Number
AT91C_MCI_RSPTYP          EQU (0x3:SHL:6) ;- (MCI) Response Type
AT91C_MCI_RSPTYP_NO       EQU (0x0:SHL:6) ;- (MCI) No response
AT91C_MCI_RSPTYP_48       EQU (0x1:SHL:6) ;- (MCI) 48-bit response
AT91C_MCI_RSPTYP_136      EQU (0x2:SHL:6) ;- (MCI) 136-bit response
AT91C_MCI_SPCMD           EQU (0x7:SHL:8) ;- (MCI) Special CMD
AT91C_MCI_SPCMD_NONE      EQU (0x0:SHL:8) ;- (MCI) Not a special CMD
AT91C_MCI_SPCMD_INIT      EQU (0x1:SHL:8) ;- (MCI) Initialization CMD
AT91C_MCI_SPCMD_SYNC      EQU (0x2:SHL:8) ;- (MCI) Synchronized CMD
AT91C_MCI_SPCMD_IT_CMD    EQU (0x4:SHL:8) ;- (MCI) Interrupt command
AT91C_MCI_SPCMD_IT_REP    EQU (0x5:SHL:8) ;- (MCI) Interrupt response
AT91C_MCI_OPDCMD          EQU (0x1:SHL:11) ;- (MCI) Open Drain Command
AT91C_MCI_MAXLAT          EQU (0x1:SHL:12) ;- (MCI) Maximum Latency for Command to respond
AT91C_MCI_TRCMD           EQU (0x3:SHL:16) ;- (MCI) Transfer CMD
AT91C_MCI_TRCMD_NO        EQU (0x0:SHL:16) ;- (MCI) No transfer
AT91C_MCI_TRCMD_START     EQU (0x1:SHL:16) ;- (MCI) Start transfer
AT91C_MCI_TRCMD_STOP      EQU (0x2:SHL:16) ;- (MCI) Stop transfer
AT91C_MCI_TRDIR           EQU (0x1:SHL:18) ;- (MCI) Transfer Direction
AT91C_MCI_TRTYP           EQU (0x3:SHL:19) ;- (MCI) Transfer Type
AT91C_MCI_TRTYP_BLOCK     EQU (0x0:SHL:19) ;- (MCI) Block Transfer type
AT91C_MCI_TRTYP_MULTIPLE  EQU (0x1:SHL:19) ;- (MCI) Multiple Block transfer type
AT91C_MCI_TRTYP_STREAM    EQU (0x2:SHL:19) ;- (MCI) Stream transfer type
;- -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
AT91C_MCI_CMDRDY          EQU (0x1:SHL:0) ;- (MCI) Command Ready flag
AT91C_MCI_RXRDY           EQU (0x1:SHL:1) ;- (MCI) RX Ready flag
AT91C_MCI_TXRDY           EQU (0x1:SHL:2) ;- (MCI) TX Ready flag
AT91C_MCI_BLKE            EQU (0x1:SHL:3) ;- (MCI) Data Block Transfer Ended flag
AT91C_MCI_DTIP            EQU (0x1:SHL:4) ;- (MCI) Data Transfer in Progress flag
AT91C_MCI_NOTBUSY         EQU (0x1:SHL:5) ;- (MCI) Data Line Not Busy flag
AT91C_MCI_ENDRX           EQU (0x1:SHL:6) ;- (MCI) End of RX Buffer flag
AT91C_MCI_ENDTX           EQU (0x1:SHL:7) ;- (MCI) End of TX Buffer flag
AT91C_MCI_RXBUFF          EQU (0x1:SHL:14) ;- (MCI) RX Buffer Full flag
AT91C_MCI_TXBUFE          EQU (0x1:SHL:15) ;- (MCI) TX Buffer Empty flag
AT91C_MCI_RINDE           EQU (0x1:SHL:16) ;- (MCI) Response Index Error flag
AT91C_MCI_RDIRE           EQU (0x1:SHL:17) ;- (MCI) Response Direction Error flag
AT91C_MCI_RCRCE           EQU (0x1:SHL:18) ;- (MCI) Response CRC Error flag
AT91C_MCI_RENDE           EQU (0x1:SHL:19) ;- (MCI) Response End Bit Error flag
AT91C_MCI_RTOE            EQU (0x1:SHL:20) ;- (MCI) Response Time-out Error flag
AT91C_MCI_DCRCE           EQU (0x1:SHL:21) ;- (MCI) data CRC Error flag
AT91C_MCI_DTOE            EQU (0x1:SHL:22) ;- (MCI) Data timeout Error flag
AT91C_MCI_OVRE            EQU (0x1:SHL:30) ;- (MCI) Overrun flag
AT91C_MCI_UNRE            EQU (0x1:SHL:31) ;- (MCI) Underrun flag
;- -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
;- -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
;- -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR USB Device Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_UDP
UDP_NUM         #  4 ;- Frame Number Register
UDP_GLBSTATE    #  4 ;- Global State Register
UDP_FADDR       #  4 ;- Function Address Register
                #  4 ;- Reserved
UDP_IER         #  4 ;- Interrupt Enable Register
UDP_IDR         #  4 ;- Interrupt Disable Register
UDP_IMR         #  4 ;- Interrupt Mask Register
UDP_ISR         #  4 ;- Interrupt Status Register
UDP_ICR         #  4 ;- Interrupt Clear Register
                #  4 ;- Reserved
UDP_RSTEP       #  4 ;- Reset Endpoint Register
                #  4 ;- Reserved
UDP_CSR         # 32 ;- Endpoint Control and Status Register
UDP_FDR         # 32 ;- Endpoint FIFO Data Register
;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
AT91C_UDP_FRM_NUM         EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
AT91C_UDP_FRM_ERR         EQU (0x1:SHL:16) ;- (UDP) Frame Error
AT91C_UDP_FRM_OK          EQU (0x1:SHL:17) ;- (UDP) Frame OK
;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
AT91C_UDP_FADDEN          EQU (0x1:SHL:0) ;- (UDP) Function Address Enable
AT91C_UDP_CONFG           EQU (0x1:SHL:1) ;- (UDP) Configured
AT91C_UDP_RMWUPE          EQU (0x1:SHL:2) ;- (UDP) Remote Wake Up Enable
AT91C_UDP_RSMINPR         EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host
;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
AT91C_UDP_FADD            EQU (0xFF:SHL:0) ;- (UDP) Function Address Value
AT91C_UDP_FEN             EQU (0x1:SHL:8) ;- (UDP) Function Enable
;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
AT91C_UDP_EPINT0          EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt
AT91C_UDP_EPINT1          EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt
AT91C_UDP_EPINT2          EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt
AT91C_UDP_EPINT3          EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt
AT91C_UDP_EPINT4          EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 Interrupt
AT91C_UDP_EPINT5          EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 Interrupt
AT91C_UDP_EPINT6          EQU (0x1:SHL:6) ;- (UDP) Endpoint 6 Interrupt
AT91C_UDP_EPINT7          EQU (0x1:SHL:7) ;- (UDP) Endpoint 7 Interrupt
AT91C_UDP_RXSUSP          EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt
AT91C_UDP_RXRSM           EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt
AT91C_UDP_EXTRSM          EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt
AT91C_UDP_SOFINT          EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt
AT91C_UDP_WAKEUP          EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt
;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
AT91C_UDP_ENDBUSRES       EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt
;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
AT91C_UDP_EP0             EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0
AT91C_UDP_EP1             EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1
AT91C_UDP_EP2             EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2
AT91C_UDP_EP3             EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3
AT91C_UDP_EP4             EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4
AT91C_UDP_EP5             EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5
AT91C_UDP_EP6             EQU (0x1:SHL:6) ;- (UDP) Reset Endpoint 6
AT91C_UDP_EP7             EQU (0x1:SHL:7) ;- (UDP) Reset Endpoint 7
;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
AT91C_UDP_TXCOMP          EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR
AT91C_UDP_RX_DATA_BK0     EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0
AT91C_UDP_RXSETUP         EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints)
AT91C_UDP_ISOERROR        EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints)
AT91C_UDP_TXPKTRDY        EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready
AT91C_UDP_FORCE