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                         PSDsoft Express Version 8.21
                         Summary of Design Assistant
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PROJECT    : combine                       DATE : 06/06/2006
DEVICE     : uPSD3254A                     TIME : 15:19:58
MCU/DSP    : uPSD32XX    
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Initial setting for Program and Data Space:
===========================================

  Main PSD flash memory will reside in this space at power-up:      Program Space Only
  Secondary PSD flash memory will reside in this space at power-up: Data Space Only

Pin Definitions:
================

Pin          Signal                    Pin
Name         Name                      Type
------------ ------------------------- ------------
pa7          LCD_EN                    External chip select - Active-Lo
pa6          SCK                       GP I/O mode 
pa4          KEYSELECT                 GP I/O mode 
pa3          Y0102                     Combinatorial
pa2          Y02                       Logic or address
pa1          Y01                       Logic or address
pa0          la0                       Latched address out - Low byte
pb7          PTT                       GP I/O mode 
pb4          SW3                       GP I/O mode 
pb3          SW2                       GP I/O mode 
pb2          KC1                       GP I/O mode 
pb1          KB1                       GP I/O mode 
pb0          KA1                       GP I/O mode 
pc7          EN8870                    External chip select - Active Hi
tdo          tdo                       Dedicated JTAG - TDO
tdi          tdi                       Dedicated JTAG - TDI
pc4          _terr                     Dedicated JTAG - /TERR
pc3          tstat                     Dedicated JTAG - TSTAT
pc2          EN922                     External chip select - Active-Lo
tck          tck                       Dedicated JTAG - TCK
tms          tms                       Dedicated JTAG - TMS
pd2          INT922_REV                Combinatorial
pd1          INT922_IN                 Logic or address
ale          ale                       ALE output  
p4.7         BACKLIGHT                 GP I/O mode 
p4.6         p4_6                      GP I/O mode 
p4.5         p4_5                      GP I/O mode 
p4.4         p4_4                      GP I/O mode 
p4.2         LCD_RST                   GP I/O mode 
p4.1         CDMA_RST                  GP I/O mode 
p4.0         GPS_RST                   GP I/O mode 
p3.7         HOLD                      GP I/O mode 
p3.6         SCI                       GP I/O mode 
p3.5         SDI                       GP I/O mode 
p3.4         SDO                       GP I/O mode 
p3.3         INT922                    Int1 or Timer1 Gate
p3.2         DTMF_INT                  Int0 or Timer0 Gate
p3.1         GPS_TxD                   UART1 TxD   
p3.0         GPS_RxD                   UART1 RxD   
p1.7         RUN_LIGHT                 GP I/O mode 
p1.6         BEEP                      GP I/O mode 
p1.5         GREEN_LIGHT               GP I/O mode 
p1.4         RED_LIGHT                 GP I/O mode 
p1.3         CDMA_TxD                  UART2 TxD   
p1.2         CDMA_RxD                  UART2 RxD   
p1.1         p1_1                      GP I/O mode 
p1.0         CDMAONOFF                 GP I/O mode 
a11          a11                       Address line
a10          a10                       Address line
a9           a9                        Address line
a8           a8                        Address line
ad7          a7                        Data/Address line
ad6          a6                        Data/Address line
ad5          a5                        Data/Address line
ad4          a4                        Data/Address line
ad3          a3                        Data/Address line
ad2          a2                        Data/Address line
ad1          a1                        Data/Address line
ad0          a0                        Data/Address line
_Reset_In    _Reset_In                 Reset In    
Vref         VREF                      VREF input  
_rd          _rd                       Bus control output
_psen        _psen                     Bus control output
_wr          _wr                       Bus control output
USB-         USB_minus                 USB- bus    
USB+         USB_plus                  USB+ bus    
Xtal1        Xtal1                     Xtal1       
Xtal2        Xtal2                     Xtal2       

User defined nodes:
===================

None defined

Page Register settings:
=======================

pgr0 is used for paging
pgr1 is used for paging
pgr2 is used for paging
pgr3 is not used
pgr4 is not used
pgr5 is not used
pgr6 is not used
pgr7 is not used

Equations:
==========

rs0 = ((address >= ^h0200) & (address <= ^h81FF));
csiop = ((address >= ^h0000) & (address <= ^h00FF));
fs0 = ((address >= ^h0000) & (address <= ^h7FFF));
fs1 = ((address >= ^h8000) & (address <= ^hFFFF));
! LCD_EN = ((address >= ^h0100) & (address <= ^h0102) & (!_rd))
     # ((address >= ^h0100) & (address <= ^h0102) & (!_wr));
EN8870 = ((address >= ^h0105) & (address <= ^h0106) & (!_rd));
! EN922 = ((address >= ^h010A) & (address <= ^h011F) & (!_rd));
Y0102 = !(Y01 & Y02);
Y0102.oe = Vcc;
INT922_REV = !INT922_IN;
INT922_REV.oe = Vcc;