LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY rom IS
  PORT(address:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
       sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       data:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END rom;
ARCHITECTURE romsin OF rom IS
  SIGNAL addresstemp:STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
  PROCESS(address,sel)
  BEGIN
        addresstemp<=address;
       IF (sel="00") THEN
         IF(address<180) THEN
             data<=(OTHERS=>'1');
         ELSE
             data<=(OTHERS=>'0');
         END IF;
       ELSIF(sel="01") THEN
         IF(address<180) THEN
             data<=address(7 DOWNTO 0);
         ELSE
             addresstemp<=addresstemp-180;
             data<=addresstemp(7 DOWNTO 0);
         END IF;
       ELSE
             data<='0' & address(7 DOWNTO 1);
       END IF;
  END PROCESS ;
END romsin;