;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source          : Cstartup.arm
;- Object               : Generic CStartup for ARM ADS 1.2 and EB40A
;- Compilation flag     : None
;-
;- 1.0 17/Feb/03 JPP     : Creation
;------------------------------------------------------------------------------


		INCLUDE		include/AT91R40008.inc

;--------------------------------
;- ARM Core Mode and Status Bits
;--------------------------------

ARM_MODE_USER           EQU     0x10
ARM_MODE_FIQ            EQU     0x11
ARM_MODE_IRQ            EQU     0x12
ARM_MODE_SVC            EQU     0x13
ARM_MODE_ABORT          EQU     0x17
ARM_MODE_UNDEF          EQU     0x1B
ARM_MODE_SYS            EQU     0x1F

I_BIT                   EQU     0x80
F_BIT                   EQU     0x40
T_BIT                   EQU     0x20


;- Get the start Ram address
;- For Flash definition
      IF  :DEF:FLASH
TOP_INTERNAL_MEMORY  EQU   AT91C_SRAM_BEFORE_REMAP
      ELSE                                ; not use FLASH USE ICE
;- For Ice definition
TOP_INTERNAL_MEMORY	 EQU	AT91C_SRAM_AFTER_REMAP
      ENDIF                               ; endif SEMIHOSTING

;------------------------------------------------------------------------------
;- Area Definition
;------------------------------------------------------------------------------

                AREA        reset, CODE, READONLY
                ENTRY
				EXPORT		entry
entry
;------------------------------------------------------------------------------
;- Exception vectors ( before Remap )
;------------------------------------
;- These vectors can be read at address 0 or at RAM address
;- They ABSOLUTELY requires to be in relative addressing mode in order to
;- guarantee a valid jump. For the moment, all are just looping.
;- If an exception occurs before remap, this would result in an infinite loop.
;- To ensure if a exception occurs before start application to infinite loop.
;------------------------------------------------------------------------------
                B           InitReset           ; Reset handler
undefvec
                B           undefvec            ; Undefined Instruction
swivec
                B           swivec              ; Software Interrupt
pabtvec
                B           pabtvec             ; Prefetch Abort
dabtvec
                B           dabtvec             ; Data Abort
rsvdvec
                B           rsvdvec             ; reserved
irqvec
                B           irqvec              ; IRQ
fiqvec
                B           fiqvec              ; FIQ

;------------------------------------------------------------------------------
;- Exception vectors ( after cstartup execution )
;------------------------------------
;- These vectors are read at RAM address after the remap command is performed in
;- the EBI. As they will be relocated at address 0x0 to be effective, a
;- RELATIVE addressing is FORBIDDEN. The only possibility to get an absolute
;- addressing for an ARM vector is to read a PC relative value at a defined
;- offset. It is easy to reserve the locations 0x20 to 0x3C (the 8 next
;- vectors) for storing the absolute exception handler address.
;- The AIC vectoring access vectors are saved in the interrupt and fast
;- interrupt ARM vectors. So, only 5 offsets are required (reserved vector
;- offset is never used).
;- The provisory handler addresses are defined on infinite loop and can be
;- modified at any time.
;- Note also that the reset is only accessible by a jump from the application
;- to 0. It is an actual software reset.
;- As the 13 (8+5) first location are used by the vectors, the read/write link
;- address must be defined from 0x34 if internal data mapping is required.
;- (use for that the option -rw- base=0x34
;------------------------------------------------------------------------------
    EXPORT VectorTable

VectorTable
                ldr         pc, [pc, #&18]          ; SoftReset
                ldr         pc, [pc, #&18]          ; UndefHandler
                ldr         pc, [pc, #&18]          ; SWIHandler
                ldr         pc, [pc, #&18]          ; PrefetchAbortHandler
                ldr         pc, [pc, #&18]          ; DataAbortHandler
                nop                                 ; Reserved
                ldr         pc, [pc,#-0xF20]        ; IRQ : read the AIC
                ldr         pc, [pc,#-0xF20]        ; FIQ : read the AIC

;- There are only 5 offsets as the vectoring is used.
                DCD         SoftReset
                DCD         UndefHandler
                DCD         SWIHandler
                DCD         PrefetchAbortHandler
                DCD         DataAbortHandler

;- Vectoring Execution function run at absolute address
SoftReset
                b           SoftReset
UndefHandler
                b           UndefHandler
SWIHandler
                b           SWIHandler
PrefetchAbortHandler
                b           PrefetchAbortHandler
DataAbortHandler
                b           DataAbortHandler
;--------------------
;- The reset handler
;--------------------
InitReset
;------------------------------------------------------------------------------
;- Low level Init (APMC, AIC, EBI, ....) by C function AT91F_LowLevelInit
;------------------------------------------------------------------------------
            IMPORT   AT91F_LowLevelInit

TOP_EXCEPTION_STACK  EQU (TOP_INTERNAL_MEMORY+AT91C_SRAM_AFTER_REMAP_SIZE)
;- minimum  C initialization

            ldr     r13,=TOP_EXCEPTION_STACK    ; temporary stack in internal Ram
			ldr		r1,=TOP_INTERNAL_MEMORY
            add     r0, pc,#-(8+.-VectorTable)  ; @ where to read values (relative)
            bl      AT91F_LowLevelInit

;--------------------------------------------
;- Remap Command and jump on ABSOLUTE address
;--------------------------------------------

            ldr     r12, PtInitRemap        ; Get the real jump address ( after remap )
            mov     r1,#AT91C_EBI_RCB       ; Get the REMAP value
            str     r1, [r0]                ; Store the complete image with the remap command

;- Jump to LINK address at its absolute address
            mov     pc, r12                 ; Jump and break the pipeline

PtInitRemap
            DCD     InitRemap               ; Address where to jump after REMAP
;------------------------------------------------------------------------------
;- The Reset Handler after Remap
;-------------------------------
;- From here, the code is executed from its link address, ie. 0x100 0000.
;------------------------------------------------------------------------------
InitRemap

;------------------------------------------------------------------------------
;- Stack Sizes Definition
;------------------------
;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
;- the vectoring. This assume that the IRQ_ENTRY/IRQ_EXIT macro are used.
;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
;- Fast Interrupt not requires stack If in your application it required you must
;- be define here.
;- Other stacks are defined by default to save one word each.
;- The System stack size is not defined and is limited by the free internal
;- SRAM.
;- User stack size is not defined and is limited by the free external SRAM.
;------------------------------------------------------------------------------

IRQ_STACK_SIZE      EQU     (2*8*4)     ; 2 words per interrupt priority level
FIQ_STACK_SIZE      EQU     (0*4)       ; 0 words
ABT_STACK_SIZE      EQU     (1*4)       ; 1 word
UND_STACK_SIZE      EQU     (1*4)       ; 1 word


;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------------
                ldr     r0, =AT91C_SRAM_AFTER_REMAP_SIZE

;- Set up Fast Interrupt Mode and set FIQ Mode Stack
                msr     CPSR_c, #ARM_MODE_FIQ:OR:I_BIT:OR:F_BIT
                mov     r13, r0                     ; Init stack FIQ
                sub     r0, r0, #FIQ_STACK_SIZE

;- Set up Interrupt Mode and set IRQ Mode Stack
                msr     CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
                mov     r13, r0                     ; Init stack IRQ
                sub     r0, r0, #IRQ_STACK_SIZE

;- Set up Abort Mode and set Abort Mode Stack
                msr     CPSR_c, #ARM_MODE_ABORT:OR:I_BIT:OR:F_BIT
                mov     r13, r0                     ; Init stack Abort
                sub     r0, r0, #ABT_STACK_SIZE

;- Set up Undefined Instruction Mode and set Undef Mode Stack
                msr     CPSR_c, #ARM_MODE_UNDEF:OR:I_BIT:OR:F_BIT
                mov     r13, r0                     ; Init stack Undef
                sub     r0, r0, #UND_STACK_SIZE

;- Set up Supervisor Mode and set Supervisor Mode Stack
                msr     CPSR_c, #ARM_MODE_SVC:OR:I_BIT:OR:F_BIT
                mov     r13, r0                     ; Init stack Sup

;------------------------------------------------------------------------------
;- Before Init C Initialize C variables you can copy the from FLASH to RAM
;------------------------------------------------------------------------------

;Enable interrupt
            msr     CPSR_c, #ARM_MODE_SVC :OR: F_BIT

;------------------------------------------------------------------------------
;- Branch on C code Main function (with interworking)
;----------------------------------------------------
;- Branch must be performed by an interworking call as either an ARM or Thumb
;- main C function must be supported. This makes the code not position-
;- independent. A Branch with link would generate errors
;------------------------------------------------------------------------------
                IMPORT      __main

                ldr         r0, =__main
                mov         lr, pc
                bx          r0

;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;- Could jump on Software Reset ( B 0x0 ).
;------------------------------------------------------------------------------
End
            b           End




;------------------------------------------------------------------------------
;- Manage exception
;---------------
;- The exception must be ensure in ARM mode
;------------------------------------------------------------------------------

            EXPORT AT91F_Default_FIQ_handler
AT91F_Default_FIQ_handler
            b     AT91F_Default_FIQ_handler


    		EXPORT AT91F_Default_IRQ_handler
AT91F_Default_IRQ_handler
            b     AT91F_Default_IRQ_handler

	         EXPORT AT91F_Spurious_handler
AT91F_Spurious_handler
            b     AT91F_Spurious_handler

    END