?? decoder.v
字號:
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_PSW;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`XCH_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_I;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_XCH;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_1;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_Y;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`XCHD :begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_I;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_XCH;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_Y;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`XRL_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_XOR;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
//op_code [7:0]
`ADD_D : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ADD_C : begin
ram_rd_sel = 2'bxx;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ADDC_D : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_PSW;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ADDC_C : begin
ram_rd_sel = 2'bxx;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_PSW;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ANL_D : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_AND;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ANL_C : begin
ram_rd_sel = 2'bxx;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_AND;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ANL_DD : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_D;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_AND;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ANL_DC : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_D;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_RAM;
alu_op = `ALU_AND;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP3;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ANL_B : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_AND;
wr = 1'b0;
psw_set = `PS_CY;
cy_sel = `CY_PSW;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ANL_NB : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_RR;
wr = 1'b0;
psw_set = `PS_CY;
cy_sel = `CY_PSW;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_D : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_SUB;
wr = 1'b0;
psw_set = `PS_CY;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_C : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_SUB;
wr = 1'b0;
psw_set = `PS_CY;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CLR_A : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_ACC;
alu_op = `ALU_SUB;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_PC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CLR_C : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_CY;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_PC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CLR_B : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_D;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_PC;
comp_sel = `CSS_DC;
wr_bit = 1'b1;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CPL_A : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOT;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP3;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CPL_C : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOT;
wr = 1'b0;
psw_set = `PS_CY;
cy_sel = `CY_PSW;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP3;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CPL_B : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_D;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOT;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_RAM;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP3;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b1;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`DA : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_DC;
alu_op = `ALU_DA;
wr = 1'b1;
psw_set = `PS_CY;
cy_sel = `CY_DC;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b1;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`DEC_A : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_ZERO;
alu_op = `ALU_SUB;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_1;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
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