?? registerfile.v
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`include "Def_RegisterFile.v"
`include "Def_Mode.v"
//this register file support 4 reads and 3 write
module RegisterFile( //change of state
in_IfChangeState, //this port means access other bank of register, only SWI or FIQ or IRQ or UND or ABT use it
in_MemAccessUserBankRegister2WB, //access user bank, use only by LDM/STM
in_ChangeStateAction, //which bank of register to access
//SWI or FIQ or IRQ or UND or ABT only use r14 as link register
//LDM/STM use user bank only
//other read port
in_LeftReadEnable,
in_LeftReadRegisterNumber,
out_LeftReadBus,
in_RightReadEnable,
in_RightReadRegisterNumber,
out_RightReadBus,
in_ThirdReadEnable,
in_ThirdReadRegisterNumber,
out_ThirdReadBus,
in_FourthReadEnable,
in_FourthReadRegisterNumber,
out_FourthReadBus,
in_WriteEnable,
in_WriteRegisterNumber,
in_WriteBus,
in_SecondWriteEnable,
in_SecondWriteRegisterNumber,
in_SecondWriteBus,
in_ThirdWriteEnable,
in_ThirdWriteRegisterNumber,
in_ThirdWriteBus,
//the processor mode
in_ProcessorMode,
clock,
reset
);
//////////////////////////////////////////////////
//////////////////////////////////////////////////
// port declaration //
//////////////////////////////////////////////////
//////////////////////////////////////////////////
input in_IfChangeState;
input in_MemAccessUserBankRegister2WB;
input [4:0] in_ChangeStateAction;
input in_LeftReadEnable,in_RightReadEnable,in_ThirdReadEnable,in_FourthReadEnable,in_WriteEnable,in_SecondWriteEnable,in_ThirdWriteEnable;
input [`Def_RegisterSelectWidth-1:0] in_LeftReadRegisterNumber,in_RightReadRegisterNumber,in_ThirdReadRegisterNumber,in_FourthReadRegisterNumber,in_WriteRegisterNumber,in_SecondWriteRegisterNumber,in_ThirdWriteRegisterNumber;
output [`WordWidth-1:0] out_LeftReadBus,out_RightReadBus,out_ThirdReadBus,out_FourthReadBus;
reg [`WordWidth-1:0] out_LeftReadBus,out_RightReadBus,out_ThirdReadBus,out_FourthReadBus;
input [`WordWidth-1:0] in_WriteBus,in_SecondWriteBus,in_ThirdWriteBus;
input [4:0] in_ProcessorMode;
input clock,reset;
//////////////////////////////////////////////////
//////////////////////////////////////////////////
// memory for registers //
//////////////////////////////////////////////////
//////////////////////////////////////////////////
//16 general register
reg [`WordWidth-1:0] Registers0;
reg [`WordWidth-1:0] Registers1;
reg [`WordWidth-1:0] Registers2;
reg [`WordWidth-1:0] Registers3;
reg [`WordWidth-1:0] Registers4;
reg [`WordWidth-1:0] Registers5;
reg [`WordWidth-1:0] Registers6;
reg [`WordWidth-1:0] Registers7;
reg [`WordWidth-1:0] Registers8;
reg [`WordWidth-1:0] Registers9;
reg [`WordWidth-1:0] Registers10;
reg [`WordWidth-1:0] Registers11;
reg [`WordWidth-1:0] Registers12;
reg [`WordWidth-1:0] Registers13;
reg [`WordWidth-1:0] Registers14;
reg [`WordWidth-1:0] Registers15;
//7 reg for FIQ mode
reg [`WordWidth-1:0] Registers8_FIQ;
reg [`WordWidth-1:0] Registers9_FIQ;
reg [`WordWidth-1:0] Registers10_FIQ;
reg [`WordWidth-1:0] Registers11_FIQ;
reg [`WordWidth-1:0] Registers12_FIQ;
reg [`WordWidth-1:0] Registers13_FIQ;
reg [`WordWidth-1:0] Registers14_FIQ;
//2 reg for supervisor mode
reg [`WordWidth-1:0] Registers13_SVC;
reg [`WordWidth-1:0] Registers14_SVC;
//2 reg for abort mode
reg [`WordWidth-1:0] Registers13_ABT;
reg [`WordWidth-1:0] Registers14_ABT;
//2 reg for IRQ mode
reg [`WordWidth-1:0] Registers13_IRQ;
reg [`WordWidth-1:0] Registers14_IRQ;
//2 reg undefined instruction mode
reg [`WordWidth-1:0] Registers13_UND;
reg [`WordWidth-1:0] Registers14_UND;
//Def_LocalForwardRegister
reg [`WordWidth-1:0] LocalForwardRegister;
integer ssycnt;
//left read
always @(Registers0 or
Registers1 or
Registers2 or
Registers3 or
Registers4 or
Registers5 or
Registers6 or
Registers7 or
Registers8 or
Registers9 or
Registers10 or
Registers11 or
Registers12 or
Registers13 or
Registers14 or
Registers15 or
Registers8_FIQ or
Registers9_FIQ or
Registers10_FIQ or
Registers11_FIQ or
Registers12_FIQ or
Registers13_FIQ or
Registers14_FIQ or
Registers13_SVC or
Registers14_SVC or
Registers13_ABT or
Registers14_ABT or
Registers13_IRQ or
Registers14_IRQ or
Registers13_UND or
Registers14_UND or
LocalForwardRegister or
in_ProcessorMode or
in_LeftReadEnable or
in_LeftReadRegisterNumber or
in_IfChangeState or
in_ChangeStateAction or
in_MemAccessUserBankRegister2WB
)
begin
if(in_LeftReadEnable==1'b1)
begin
case (in_LeftReadRegisterNumber)
8'b0000_0000:
out_LeftReadBus=Registers0;
8'b0000_0001:
out_LeftReadBus=Registers1;
8'b0000_0010:
out_LeftReadBus=Registers2;
8'b0000_0011:
out_LeftReadBus=Registers3;
8'b0000_0100:
out_LeftReadBus=Registers4;
8'b0000_0101:
out_LeftReadBus=Registers5;
8'b0000_0110:
out_LeftReadBus=Registers6;
8'b0000_0111:
out_LeftReadBus=Registers7;
8'b0000_1000:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_LeftReadBus=Registers8;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_LeftReadBus=Registers8_FIQ;
else
out_LeftReadBus=Registers8;
end
8'b0000_1001:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_LeftReadBus=Registers9;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_LeftReadBus=Registers9_FIQ;
else
out_LeftReadBus=Registers9;
end
8'b0000_1010:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_LeftReadBus=Registers10;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_LeftReadBus=Registers10_FIQ;
else
out_LeftReadBus=Registers10;
end
8'b0000_1011:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_LeftReadBus=Registers11;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_LeftReadBus=Registers11_FIQ;
else
out_LeftReadBus=Registers11;
end
8'b0000_1100:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_LeftReadBus=Registers12;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_LeftReadBus=Registers12_FIQ;
else
out_LeftReadBus=Registers12;
end
8'b0000_1101:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_LeftReadBus=Registers13;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_LeftReadBus=Registers13_FIQ;
else if(in_ProcessorMode==`MODE_SVC)
out_LeftReadBus=Registers13_SVC;
else if(in_ProcessorMode==`MODE_ABT)
out_LeftReadBus=Registers13_ABT;
else if(in_ProcessorMode==`MODE_IRQ)
out_LeftReadBus=Registers13_IRQ;
else if(in_ProcessorMode==`MODE_UND)
out_LeftReadBus=Registers13_UND;
else//normal
out_LeftReadBus=Registers13;
end
8'b0000_1110:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
out_LeftReadBus=Registers14;
else if(in_IfChangeState==1'b1)
begin
case(in_ChangeStateAction)
`MODE_FIQ:
out_LeftReadBus=Registers14_FIQ;
`MODE_SVC:
out_LeftReadBus=Registers14_SVC;
`MODE_ABT:
out_LeftReadBus=Registers14_ABT;
`MODE_IRQ:
out_LeftReadBus=Registers14_IRQ;
`MODE_UND:
out_LeftReadBus=Registers14_UND;
default:
out_LeftReadBus=Registers14;
endcase
end
else if(in_ProcessorMode==`MODE_FIQ)
out_LeftReadBus=Registers14_FIQ;
else if(in_ProcessorMode==`MODE_SVC)
out_LeftReadBus=Registers14_SVC;
else if(in_ProcessorMode==`MODE_ABT)
out_LeftReadBus=Registers14_ABT;
else if(in_ProcessorMode==`MODE_IRQ)
out_LeftReadBus=Registers14_IRQ;
else if(in_ProcessorMode==`MODE_UND)
out_LeftReadBus=Registers14_UND;
else//normal
out_LeftReadBus=Registers14;
end
8'b0000_1111:
out_LeftReadBus=Registers15;
`Def_LocalForwardRegister:
out_LeftReadBus=LocalForwardRegister;
default:
out_LeftReadBus=`WordZero;
endcase
end
else
begin
out_LeftReadBus=`WordZero;
end
end
//right read
always @(Registers0 or
Registers1 or
Registers2 or
Registers3 or
Registers4 or
Registers5 or
Registers6 or
Registers7 or
Registers8 or
Registers9 or
Registers10 or
Registers11 or
Registers12 or
Registers13 or
Registers14 or
Registers15 or
Registers8_FIQ or
Registers9_FIQ or
Registers10_FIQ or
Registers11_FIQ or
Registers12_FIQ or
Registers13_FIQ or
Registers14_FIQ or
Registers13_SVC or
Registers14_SVC or
Registers13_ABT or
Registers14_ABT or
Registers13_IRQ or
Registers14_IRQ or
Registers13_UND or
Registers14_UND or
LocalForwardRegister or
in_ProcessorMode or
in_RightReadEnable or
in_RightReadRegisterNumber or
in_IfChangeState or
in_ChangeStateAction or
in_MemAccessUserBankRegister2WB
)
begin
if(in_RightReadEnable==1'b1)
begin
case (in_RightReadRegisterNumber)
8'b0000_0000:
out_RightReadBus=Registers0;
8'b0000_0001:
out_RightReadBus=Registers1;
8'b0000_0010:
out_RightReadBus=Registers2;
8'b0000_0011:
out_RightReadBus=Registers3;
8'b0000_0100:
out_RightReadBus=Registers4;
8'b0000_0101:
out_RightReadBus=Registers5;
8'b0000_0110:
out_RightReadBus=Registers6;
8'b0000_0111:
out_RightReadBus=Registers7;
8'b0000_1000:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_RightReadBus=Registers8;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_RightReadBus=Registers8_FIQ;
else
out_RightReadBus=Registers8;
end
8'b0000_1001:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_RightReadBus=Registers9;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_RightReadBus=Registers9_FIQ;
else
out_RightReadBus=Registers9;
end
8'b0000_1010:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_RightReadBus=Registers10;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_RightReadBus=Registers10_FIQ;
else
out_RightReadBus=Registers10;
end
8'b0000_1011:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_RightReadBus=Registers11;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_RightReadBus=Registers11_FIQ;
else
out_RightReadBus=Registers11;
end
8'b0000_1100:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_RightReadBus=Registers12;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_RightReadBus=Registers12_FIQ;
else
out_RightReadBus=Registers12;
end
8'b0000_1101:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
begin
out_RightReadBus=Registers13;
end
else if(in_ProcessorMode==`MODE_FIQ)
out_RightReadBus=Registers13_FIQ;
else if(in_ProcessorMode==`MODE_SVC)
out_RightReadBus=Registers13_SVC;
else if(in_ProcessorMode==`MODE_ABT)
out_RightReadBus=Registers13_ABT;
else if(in_ProcessorMode==`MODE_IRQ)
out_RightReadBus=Registers13_IRQ;
else if(in_ProcessorMode==`MODE_UND)
out_RightReadBus=Registers13_UND;
else//normal
out_RightReadBus=Registers13;
end
8'b0000_1110:
begin
if(in_MemAccessUserBankRegister2WB==1'b1)
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