?? decoder_arm.v
字號(hào):
end
else
begin
out_MEMType=`MEMType_Null;
out_MEMTargetRegister=`Def_LinkRegister;
end
//simple thread of mem stage
out_SimpleMEMType=`MEMType_MovMain;
out_SimpleMEMTargetRegister=LeftRegisterNumber;
end
else
begin
//no need to write back
//so just write base value to Def_LocalForwardRegister
out_ALUTargetRegister=`Def_LocalForwardRegister;
//main thread of mem stage
out_MEMEnable=1'b1;
//always load word
if(IfCurrentRegAccessByLDMSTM==1'b1)
begin
out_MEMType=`MEMType_LoadSimpleWord;
if({4'b0000,DecRegNumber[3:0]}==`Def_PCNumber)
out_MEMTargetRegister=`Def_LinkRegister;
else
out_MEMTargetRegister={4'b0000,DecRegNumber[3:0]};
end
else
begin
out_MEMType=`MEMType_Null;
out_MEMTargetRegister=`Def_LinkRegister;
end
//simple thread of mem stage
//no need to write back, so just write modified base to Def_LocalForwardRegister
out_SimpleMEMType=`MEMType_MovMain;
out_SimpleMEMTargetRegister=`Def_LocalForwardRegister;
end
end
out_IDOwnCanGo=1'b0;
out_ALUMisc[14]=1'b0;
//when target register is pc,and PC is to be load
//then tell mem stage to store this pc and wait for delayed branch signal
//out_ALUMisc[15] means store delay branch target
if({4'b0000,DecRegNumber[3:0]}==`Def_PCNumber && in_PipelineRegister_IFID[15]==1'b1)
out_ALUMisc[15]=1'b1;
else
out_ALUMisc[15]=1'b0;
//out_ALUMisc[16] means access user bank registers
if(in_IsInPrivilegedMode==1'b1 && in_PipelineRegister_IFID[15]==1'b0 && in_PipelineRegister_IFID[22]==1'b1)
out_ALUMisc[16]=1'b1;
else
out_ALUMisc[16]=1'b0;
Next_IncRegNumber=IncRegNumberAdd1;
Next_DecRegNumber=DecRegNumberSub1;
Next_PrevOperationWantWriteRegisterFromMEM=IfCurrentRegAccessByLDMSTM;
if(IfCurrentRegAccessByLDMSTM==1'b1)
Next_PrevWriteRegister={4'b0000,DecRegNumber[3:0]};
else
Next_PrevWriteRegister=`Def_LinkRegister;
end//of DecRegNumber[7:4]!=4'b1110
end//of down
else//up
begin
if(IncRegNumber[7:4]==4'b0001)
begin
//perform delayed branch
//except delay branch signal, nothing is use
out_LeftReadRegisterEnable=1'b0;
out_LeftReadRegisterNumber=LeftRegisterNumber;
out_ALULeftFromImm=1'b1;
//deal with offset
out_RightReadRegisterNumber=RightRegisterNumber;
out_RightReadRegisterEnable=1'b0;
out_ALURightFromImm=1'b1;
out_ALUExtendedImmediateValue=32'h0000_0000;
out_ALURightShiftType=`Def_ShiftType_LogicLeft;
//shift ammount is always 0
out_ALUSecondImmediateValue=`WordZero;
//third read bus will be use
out_ThirdReadRegisterEnable=1'b0;
out_ThirdReadRegisterNumber=ThirdRegisterNumber;
out_ALUThirdFromImm=1'b1;
//a valid ALU
out_ALUEnable=1'b1;
//sub 4 from current register
out_ALUType=`ALUType_Sub;
out_ALUTargetRegister=`Def_LinkRegister;
out_SimpleALUType=`ALUType_Null;
out_SimpleALUTargetRegister=`Def_LinkRegister;
//main thread of mem stage
out_MEMEnable=1'b1;
//always load word
out_MEMType=`MEMType_Null;
out_MEMTargetRegister=`Def_LinkRegister;
//simple thread of mem stage
out_SimpleMEMType=`MEMType_Null;
out_SimpleMEMTargetRegister=`Def_LinkRegister;
out_IDOwnCanGo=1'b1;
//out_ALUMisc[14] means delay branch
if(in_PipelineRegister_IFID[15]==1'b1)
out_ALUMisc[14]=1'b1;
else
out_ALUMisc[14]=1'b0;
//out_ALUMisc[15] means store delay branch target
out_ALUMisc[15]=1'b0;
if(in_IsInPrivilegedMode==1'b1 && in_PipelineRegister_IFID[15]==1'b1 && in_PipelineRegister_IFID[22]==1'b1)
begin
//condition code valid in alu and mem stage
out_ALUPSRType=`ALUPSRType_SPSR2CPSR;
out_MEMPSRType=`MEMPSRType_WriteCPSR;
end
Next_IncRegNumber=`Def_RegisterSelectZero;
Next_DecRegNumber=`Def_RegisterSelectAllOne;
Next_PrevOperationWantWriteRegisterFromMEM=1'b0;
Next_PrevWriteRegister=`Def_LinkRegister;
end//of IncRegNumber[7:4]==4'b0001
else
begin
out_LeftReadRegisterEnable=1'b1;
//if write back is need, then just read left register as base
//if write back is not need and it is the first access ,also read left register as base
// if write back is not need and it is not the first access, then just use LocalForwardRegister
if(in_PipelineRegister_IFID[21]==1'b1 || IsFirstAccess==1'b1)
out_LeftReadRegisterNumber=LeftRegisterNumber;
else
out_LeftReadRegisterNumber=`Def_LocalForwardRegister;
//left operand are not from immediate
out_ALULeftFromImm=1'b0;
//deal with offset
//offset come from imm in instruction
out_RightReadRegisterNumber=RightRegisterNumber;
out_RightReadRegisterEnable=1'b0;
out_ALURightFromImm=1'b1;
//imm act as offset
if(IfCurrentRegAccessByLDMSTM==1'b1)
out_ALUExtendedImmediateValue=32'h0000_0004;
else
out_ALUExtendedImmediateValue=32'h0000_0000;
out_ALURightShiftType=`Def_ShiftType_LogicLeft;
//shift ammount is always 0
out_ALUSecondImmediateValue=`WordZero;
//third read bus will be use
out_ThirdReadRegisterEnable=1'b0;
out_ThirdReadRegisterNumber=ThirdRegisterNumber;
out_ALUThirdFromImm=1'b1;
//a valid ALU
out_ALUEnable=1'b1;
//sub 4 from current register
out_ALUType=`ALUType_Add;
//deal with the case of pre or post index
if(in_PipelineRegister_IFID[24]==1'b1)
begin
//pre index
//first perform alu then use result as the address to load
out_SimpleALUType=`ALUType_Null;
out_SimpleALUTargetRegister=`Def_LinkRegister;
if(in_PipelineRegister_IFID[21]==1'b1)
begin
//write back alu result to base register
out_ALUTargetRegister=LeftRegisterNumber;
//main thread of mem stage
out_MEMEnable=1'b1;
//always load word
if(IfCurrentRegAccessByLDMSTM==1'b1)
begin
out_MEMType=`MEMType_LoadMainWord;
if({4'b0000,IncRegNumber[3:0]}==`Def_PCNumber)
out_MEMTargetRegister=`Def_LinkRegister;
else
out_MEMTargetRegister={4'b0000,IncRegNumber[3:0]};
end
else
begin
out_MEMType=`MEMType_Null;
out_MEMTargetRegister=`Def_LinkRegister;
end
//simple thread of mem stage
out_SimpleMEMType=`MEMType_MovMain;
out_SimpleMEMTargetRegister=LeftRegisterNumber;
end
else
begin
//no need to write back
//so just write base value to Def_LocalForwardRegister
out_ALUTargetRegister=`Def_LocalForwardRegister;
//main thread of mem stage
out_MEMEnable=1'b1;
//always load word
if(IfCurrentRegAccessByLDMSTM==1'b1)
begin
out_MEMType=`MEMType_LoadMainWord;
if({4'b0000,IncRegNumber[3:0]}==`Def_PCNumber)
out_MEMTargetRegister=`Def_LinkRegister;
else
out_MEMTargetRegister={4'b0000,IncRegNumber[3:0]};
end
else
begin
out_MEMType=`MEMType_Null;
out_MEMTargetRegister=`Def_LinkRegister;
end
//simple thread of mem stage
//no need to write back, so just write the modified base to Def_LocalForwardRegister
out_SimpleMEMType=`MEMType_MovMain;
out_SimpleMEMTargetRegister=`Def_LocalForwardRegister;
end
end
else
begin
//post index
//perform alu but use origin base as address to load
out_SimpleALUType=`ALUType_Mvl;
out_SimpleALUTargetRegister=`Def_LinkRegister;
if(in_PipelineRegister_IFID[21]==1'b1)
begin
out_ALUTargetRegister=LeftRegisterNumber;
//main thread of mem stage
out_MEMEnable=1'b1;
//always load word
if(IfCurrentRegAccessByLDMSTM==1'b1)
begin
out_MEMType=`MEMType_LoadSimpleWord;
if({4'b0000,IncRegNumber[3:0]}==`Def_PCNumber)
out_MEMTargetRegister=`Def_LinkRegister;
else
out_MEMTargetRegister={4'b0000,IncRegNumber[3:0]};
end
else
begin
out_MEMType=`MEMType_Null;
out_MEMTargetRegister=`Def_LinkRegister;
end
//simple thread of mem stage
out_SimpleMEMType=`MEMType_MovMain;
out_SimpleMEMTargetRegister=LeftRegisterNumber;
end
else
begin
//no need to write back
//so just write base value to Def_LocalForwardRegister
out_ALUTargetRegister=`Def_LocalForwardRegister;
//main thread of mem stage
out_MEMEnable=1'b1;
//always load word
if(IfCurrentRegAccessByLDMSTM==1'b1)
begin
out_MEMType=`MEMType_LoadSimpleWord;
if({4'b0000,IncRegNumber[3:0]}==`Def_PCNumber)
out_MEMTargetRegister=`Def_LinkRegister;
else
out_MEMTargetRegister={4'b0000,IncRegNumber[3:0]};
end
else
begin
out_MEMType=`MEMType_Null;
out_MEMTargetRegister=`Def_LinkRegister;
end
//simple thread of mem stage
//no need to write back, so just write modified base to Def_LocalForwardRegister
out_SimpleMEMType=`MEMType_MovMain;
out_SimpleMEMTargetRegister=`Def_LocalForwardRegister;
end
end
out_IDOwnCanGo=1'b0;
out_ALUMisc[14]=1'b0;
//when target register is pc,and PC is to be load
//then tell mem stage to store this pc and wait for delayed branch signal
//out_ALUMisc[15] means store delay branch target
if({4'b0000,IncRegNumber[3:0]}==`Def_PCNumber && in_PipelineRegister_IFID[15]==1'b1)
out_ALUMisc[15]=1'b1;
else
out_ALUMisc[15]=1'b0;
//out_ALUMisc[16] means access user bank registers
if(in_IsInPrivilegedMode==1'b1 && in_PipelineRegister_IFID[15]==1'b0 && in_PipelineRegister_IFID[22]==1'b1)
out_ALUMisc[16]=1'b1;
else
out_ALUMisc[16]=1'b0;
Next_IncRegNumber=IncRegNumberAdd1;
Next_DecRegNumber=DecRegNumberSub1;
Next_PrevOperationWantWriteRegisterFromMEM=IfCurrentRegAccessByLDMSTM;
if(IfCurrentRegAccessByLDMSTM==1'b1)
Next_PrevWriteRegister={4'b0000,IncRegNumber[3:0]};
else
Next_PrevWriteRegister=`Def_LinkRegister;
end//of IncRegNumber[7:4]!=4'b0001
end//of up
end//LDM
else if(`Def_IsSTM)
begin
if(in_PipelineRegister_IFID[23]==1'b0)
begin//down
if(DecRegNumber[7:4]==4'b1110)
begin
//this is stm, no need to do anything in this cycle
//just insert a blank into pipeline
out_LeftReadRegisterEnable=1'b0;
out_LeftReadRegisterNumber=LeftRegisterNumber;
out_ALULeftFromImm=1'b1;
//deal with offset
out_RightReadRegisterNumber=RightRegisterNumber;
out_RightReadRegisterEnable=1'b0;
out_ALURightFromImm=1'b1;
out_ALUExtendedImmediateValue=32'h0000_0000;
out_ALURightShiftType=`Def_ShiftType_LogicLeft;
//shift ammount is always 0
out_ALUSecondImmediateValue=`WordZero;
//third read bus will be use
out_ThirdReadRegisterEnable=1'b0;
out_ThirdReadRegisterNumber=ThirdRegisterNumber;
out_ALUThirdFromImm=1'b1;
//a valid ALU
out_ALUEnable=1'b1;
//sub 4 from current register
out_ALUType=`ALUType_Sub;
out_ALUTargetRegister=`Def_LinkRegister;
out_SimpleALUType=`ALUType_Null;
out_SimpleALUTargetRegister=`Def_LinkRegister;
//main thread of mem stage
out_MEMEnable=1'b1;
//always load word
out_MEMType=`MEMType_Null;
out_MEMTargetRegister=`Def_LinkRegister;
//simple thread of mem stage
out_SimpleMEMType=`MEMType_Null;
out_SimpleMEMTargetRegister=`Def_LinkRegister;
out_IDOwnCanGo=1'b1;
out_ALUMisc[14]=1'b0;
out_ALUMisc[15]=1'b0;
Next_IncRegNumber=`Def_RegisterSelectZero;
Next_DecRegNumber=`Def_RegisterSelectAllOne;
Next_PrevOperationWantWriteRegisterFromMEM=1'b0;
Next_PrevWriteRegister=`Def_LinkRegister;
end//of DecRegNumber[7:4]==4'b1110
else
begin
out_LeftReadRegisterEnable=1'b1;
//if write back is need, then just read left register as base
//if write back is not need and it is the first access ,also read left register as base
// if write back is not need and it is not the first access, then just use LocalForwardRegister
if(in_PipelineRegister_IFID[21]==1'b1 || IsFirstAccess?? 快捷鍵說(shuō)明
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