?? pci_arbiter_tb_di.vhd
字號(hào):
-------------------------------------------------------------------------------
-- Author: Antonio Di Rocco
-- SW Defined Radio Labs
-- SELEX COMMUNICATIONS
-- A Finmeccanica Company
-------------------------------------------------------------------------------
-- Description: Test bench for PCI arbiter.
-- - All devices may be initiator.
-- - Priority management in pure rotation arbitration
-- - Bus parking (configurable)
-------------------------------------------------------------------------------
-- Cycles description:
-- .....
-- ....
---------------------------------------------------------------------------
-- Compiler Directives
---------------------------------------------------------------------------
-- library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- UNISIM is only used for simulation so for synthesis ignore it
-- synthesis translate_off
--library XILINXCORELIB;
--library UNISIM;
--use UNISIM.all;
-- synthesis translate_on
---------------------------------------------------------------------------
-- Main Module
---------------------------------------------------------------------------
entity PCI_ARBITER_TB_DI is
generic ( MASTERS : integer := 6 );
-- port ( ------------------ System signals --------------------
-- REQ_N : in std_logic_vector(MASTERS-1 downto 0); -- BUS REQUEST signals
-- PCI_CLK : in std_logic ; -- PCI 33MHz Clock
-- PCI_RST : in std_logic; -- PCI reset
-- FRAME_N : in std_logic; -- Selected wired or
-- IRDY_N : in std_logic; -- Selected wired or
--
-- GNT_N : out std_logic_vector(MASTERS-1 downto 0) -- BUS GRANT signals
-- ) ;
end PCI_ARBITER_TB_DI ;
---------------------------------------------------------------------------
-- Main Architecture
---------------------------------------------------------------------------
architecture RTL of PCI_ARBITER_TB_DI is
-- Constants
constant PCI_CK_PERIOD : time := 30303 ps; --33MHZ
-- signal declarations
--signal SIM_END : boolean := false;
signal CLK_EN : std_logic := '0';
signal PCI_CLK_TB : std_logic := '0';
signal PCI_RST_TB : std_logic := '1';
signal FRAME_N_TB : std_logic := '1';
signal IRDY_N_TB : std_logic := '1';
signal REQ_N_TB : std_logic_vector(MASTERS-1 downto 0) := (others => '1');
signal GNT_N_TB : std_logic_vector(MASTERS-1 downto 0) ;
signal cycle1_done : std_logic := '0';
-- instantiate the top-level block
component PCI_ARBITER
port (
REQ_N : in std_logic_vector(MASTERS-1 downto 0); -- BUS REQUEST signals
PCI_CLK : in std_logic ; -- PCI 33MHz Clock
PCI_RST : in std_logic; -- PCI reset
FRAME_N : in std_logic; -- Selected wired or
IRDY_N : in std_logic; -- Selected wired or
GNT_N : out std_logic_vector(MASTERS-1 downto 0) -- BUS GRANT signals
);
end component;
begin
CLK_EN <= '1' after 1*PCI_CK_PERIOD;
PCI_RST_TB <= '0' after 3*PCI_CK_PERIOD;
PCI_CLK_TB <= not PCI_CLK_TB after PCI_CK_PERIOD/2 when (CLK_EN = '1') else '0';
DUT: PCI_ARBITER
port map (
REQ_N => REQ_N_TB,
PCI_CLK => PCI_CLK_TB,
PCI_RST => PCI_RST_TB,
FRAME_N => FRAME_N_TB,
IRDY_N => IRDY_N_TB,
GNT_N => GNT_N_TB
);
INPUT_BUSCYCLE_1: process (PCI_CLK_TB)
VARIABLE CYCLE : INTEGER := 0;
VARIABLE State : INTEGER := 0;
VARIABLE Wait_cnt : INTEGER := 0;
VARIABLE frame_size : INTEGER := 0;
--VARIABLE REQ_N_TB_var :std_logic_vector(MASTERS-1 downto 0) :="11";
begin
if (PCI_CLK_TB'event and PCI_CLK_TB = '1') then
if CYCLE = 0 then
CASE State IS
WHEN 0 =>
REQ_N_TB <= (others => '1');
FRAME_N_TB <= '1';
Wait_cnt := Wait_cnt + 1;
if (Wait_cnt = 3) then
State := 1;
Wait_cnt := 0;
end if;
WHEN 1 =>
REQ_N_TB <= "101111";
Wait_cnt := Wait_cnt + 1;
if (GNT_N_TB = "101111") then
if frame_size = 0 then
FRAME_N_TB <= '1';
frame_size := frame_size + 1;
elsif ((frame_size = 1) or (frame_size = 2)) then
FRAME_N_TB <= '0';
frame_size := frame_size + 1;
elsif frame_size = 3 then
FRAME_N_TB <= '1';
end if;
end if;
if (Wait_cnt = 6) then
State := 2;
Wait_cnt := 0;
frame_size := 0;
end if;
WHEN 2 =>
REQ_N_TB <= (others => '1');
Wait_cnt := Wait_cnt + 1;
if Wait_cnt = 1 then
State := 0;
Wait_cnt := 0;
CYCLE := 1;
end if;
WHEN OTHERS =>
NULL;
END CASE;
elsif CYCLE = 1 then
CASE State IS
WHEN 0 =>
REQ_N_TB <= (others => '1');
FRAME_N_TB <= '1';
Wait_cnt := Wait_cnt + 1;
if (Wait_cnt = 2) then
State := 1;
Wait_cnt := 0;
end if;
WHEN 1 =>
REQ_N_TB <= "011001"; -- bus request device 1,2 and 5
Wait_cnt := Wait_cnt + 1;
if (GNT_N_TB = "111101") then -- grant received from device 1 (high priority) - due to value of round prioriy shift register-
if frame_size = 0 then
FRAME_N_TB <= '1';
frame_size := frame_size + 1;
elsif ((frame_size = 1) or (frame_size = 2))then
FRAME_N_TB <= '0';
frame_size := frame_size + 1;
elsif frame_size = 3 then
FRAME_N_TB <= '1';
end if;
end if;
if (Wait_cnt = 6) then
State := 2;
Wait_cnt := 0;
frame_size := 0;
end if;
WHEN 2 =>
REQ_N_TB <= "011011"; -- mantain bus request device 2 and 5
Wait_cnt := Wait_cnt + 1;
if (GNT_N_TB = "111011") then -- grant received from device 2 (high priority) respect device 5
if frame_size = 0 then
FRAME_N_TB <= '1';
frame_size := frame_size + 1;
elsif ((frame_size = 1) or (frame_size = 2))then
FRAME_N_TB <= '0';
frame_size := frame_size + 1;
elsif frame_size = 3 then
FRAME_N_TB <= '1';
end if;
end if;
if (Wait_cnt = 8) then
State := 3;
Wait_cnt := 0;
frame_size := 0;
end if;
WHEN 3 =>
REQ_N_TB <= "011101"; -- mantain bus request device 5 plus a new request of device 1
--REQ_N_TB <= (others => '1');
Wait_cnt := Wait_cnt + 1;
if Wait_cnt = 17 then
State := 4;
Wait_cnt := 0;
end if;
WHEN 4 =>
--REQ_N_TB <= (others => '1');
REQ_N_TB <= "111101"; -- mantain bus request device 1
Wait_cnt := Wait_cnt + 1;
if Wait_cnt = 4 then
State := 0;
Wait_cnt := 0;
CYCLE := 3;
end if;
WHEN OTHERS =>
NULL;
END CASE;
end if; --CYCLE 1
end if; --clock
end process INPUT_BUSCYCLE_1;
process (PCI_CLK_TB)
begin
if (PCI_CLK_TB'event and PCI_CLK_TB = '1') then
IRDY_N_TB <= FRAME_N_TB;
end if;
end process ;
end RTL;?? 快捷鍵說(shuō)明
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